An Incremental Placement Algorithm for Building Block Layout Design Based on the O-Tree Representation

Li, Jing; Yu, Juebang; Miyashita, Hiroshi

doi:10.1093/ietfec/e88-a.12.3398

Cited by 1 publication

(2 citation statements)

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“…We include one more data point in Figures 7 and 8 for RePlace inner_num=0. 5 showing that an even faster anneal still recovers all lost quality. We also tried adding a 2 nd annealing step between expansion and compaction, but this only increased runtime and did not improve quality at all.…”

Section: Resultsmentioning

confidence: 97%

“…Approaches [3] and [6] are meant for very small netlist changes as they compute optimal locations and shift patterns for each cell individually. Floorplan shifting is used in [5], but it presumes significant available whitespace between floorplan regions. Diffusion [14], ripple moves [15], and network flow [16] algorithms are all effective approaches, but the algorithms are more complex and likely slower than RePlace.…”

Section: Related Workmentioning

confidence: 99%

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Replace: An incremental placement algorithm for field programmable gate arrays

Leong

Lemieux

2009

2009 International Conference on Field Programmable Logic and Applications

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Recompiling a large circuit after making a few logic changes is a time-consuming process. We present an incremental placement algorithm for FPGAs that is focused on extremely fast runtime for changes which can be localized. It is capable of handling multiple changes across large regions of an FPGA. This is especially useful when used with a floorplan where a modified subcircuit is instantiated several times in the design hierarchy or where several subcircuits are modified. The algorithm is simpler and faster than past approaches because its insertion and legalization steps are based on CPU-efficient shifting steps which do not continuously evaluate the impact of each move on costs. Instead, any lost quality is recovered by a fast, low-temperature anneal at the end. When 35,000 out of 50,000 LUTs are modified, the incremental placement (including fast anneal) is 7 times faster than VPR's "fast placement" from scratch with only 2% quality degradation. The key concepts utilized in the incremental placement algorithm include uses of floor-planning constraints, CPU-efficient CLB shifting, super placement grid and a tuned annealing refinement process.

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Section: Resultsmentioning

confidence: 97%