An incremental learning framework for estimating signal controllability in unit-level verification

Wen, Charles H.-P.; Wang, Li-C.; Bhadra,

doi:10.1109/iccad.2007.4397274

Cited by 3 publications

(2 citation statements)

References 13 publications

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“…The work in [28] implemented a learning and feedback method in the context of unit-level verification. While these early works showed promises of applying automatic learning to improve signal controllability, the methods were not designed to work with assembly programs directly.…”

Section: The Learning and Feedback Componentmentioning

confidence: 99%

Data mining in functional test content optimization

Wang

2015

The 20th Asia and South Pacific Design Automation Conference

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This paper reviews the data mining methodologies [1]-[4] proposed for functional test content optimization where tests are sequences of instructions or transactions. Basic machine learning concepts and the key ideas of these methodologies are explained. Challenges for implementing these methodologies in practice are illustrated. Promises are demonstrated through experimental results based on industrial verification settings.

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Section: The Learning and Feedback Componentmentioning

confidence: 99%

Data mining in functional test content optimization

Wang

2015

The 20th Asia and South Pacific Design Automation Conference

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“…Note that the behavioral abstractions for individual units are small state machines, but their construction is delicate, involving careful characterization of different design parameters. There has been some work on applying learning techniques for estimation of trace machine models [17], [18]. We are exploring the possibility of applying such techniques for learning behavioral abstractions.…”

Section: Related Work and Conclusionmentioning

confidence: 99%

Abstracting and verifying flash memories

Ray

Bhadra²

2008

2008 9th Annual Non-Volatile Memory Technology Symposium (NVMTS)

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Abstract-We present a framework for formal verification of flash cores. Flash memories cannot be verified by traditional switch-level abstractions, due to capacitive coupling induced by the presence of floating gates. We discuss a new approach to abstracting transistor networks that is agnostic to the type of transistor used in the implementation. We show how to use this abstraction to model flash memory designs. The abstractions are used for functional verification of memory cores, and can be validated through analog simulation. We have used the approach in the verification of representative NOR and a NAND flash memory cores.

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Functional verification

Wen

2009

Electronic Design Automation

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An incremental learning framework for estimating signal controllability in unit-level verification

Cited by 3 publications

References 13 publications

Data mining in functional test content optimization

Data mining in functional test content optimization

Abstracting and verifying flash memories

Functional verification

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