An In-Memory VLSI Architecture for Convolutional Neural Networks

Kang, Mingu; Lim, Soo Min; Gonugondla, Sujan K.; Shanbhag, Naresh R.

doi:10.1109/jetcas.2018.2829522

Cited by 55 publications

(31 citation statements)

References 23 publications

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“…When the precharge circuit is disabled, while the WL signal is still high, the circuit performs normal conventional read and discharges BL or BLB depending on data stored in bit cell. Many inmemory compute primitives [12], [7], [13] have shown similar kind of functional read operations where they connect the internal storage node to the bit line in order to enable analog in-memory compute.…”

Section: A Read Stabilitymentioning

confidence: 99%

“…It is worth mentioning that the ReLU operation energy consumption can be neglected compared to other operations. The delay (T V N ) and the energy (E V N ) of convolution operation in the conventional von Neumann architecture are given by equation ( 7) and (8) similar to [12]. The notations used in the equations below are described in Table III.…”

Section: System Level Analysismentioning

confidence: 99%

“…E imac ≈ M N K 2 N 2 mov [E amac + E adc /R] + P leak T in−memory (10) For a fair comparison, all array parameters are kept the same as [12] and delay and energy parameters are obtained Standby power consumption of SRAM memory from circuit simulations. The parameters used are presented in Table IV.…”

Section: System Level Analysismentioning

confidence: 99%

“…13, the total improvements in energy, delay and energy-delay product are seen to be 9.42×, 6.24× and 58.79× respectively. Since the array architecture for this work is kept similar to [12], we compare the Energy and Delay of this work and find this work to be 2.27× and 4.83× better than [12].…”

Section: System Level Analysismentioning

confidence: 99%

See 3 more Smart Citations

IMAC: In-Memory Multi-Bit Multiplication and ACcumulation in 6T SRAM Array

Ali

Jaiswal

Kodge

et al. 2020

IEEE Trans. Circuits Syst. I

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In-memory computing' is being widely explored as a novel computing paradigm to mitigate the well known memory bottleneck. This emerging paradigm aims at embedding some aspects of computations inside the memory array, thereby avoiding frequent and expensive movement of data between the compute unit and the storage memory. In-memory computing with respect to Silicon memories has been widely explored on various memory bit-cells. Embedding computation inside the 6 transistor (6T) SRAM array is of special interest since it is the most widely used on-chip memory. In this paper, we present a novel in-memory multiplication followed by accumulation operation capable of performing parallel dot products within 6T SRAM without any changes to the standard bitcell. We, further, study the effect of circuit non-idealities and process variations on the accuracy of the LeNet-5 and VGG neural network architectures against the MNIST and CIFAR-10 datasets, respectively. The proposed in-memory dot-product mechanism achieves 88.8% and 99% accuracy for the CIFAR-10 and MNIST, respectively. Compared to the standard von Neumann system, the proposed system is 6.24× better in energy consumption and 9.42× better in delay.

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Section: A Read Stabilitymentioning

confidence: 99%

Section: System Level Analysismentioning

confidence: 99%

Section: System Level Analysismentioning

confidence: 99%

Section: System Level Analysismentioning

confidence: 99%

See 2 more Smart Citations

IMAC: In-Memory Multi-Bit Multiplication and ACcumulation in 6T SRAM Array

Ali

Jaiswal

Kodge

et al. 2020

IEEE Trans. Circuits Syst. I

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“…As shown in Fig. 1(a), the first method is the multi-row reading [11,12,13,14], usually in the form of bit-line (BL / BLB) voltage, which opens multi-row at the same time through binary-weighted word-line (WL) pulse width [11,12] or weighted height [13,14]. The advantage of this method is that it can read multiple rows of data in the storage array at the same time, which increases the throughput and reduces the reading time.…”

Section: Introductionmentioning

confidence: 99%

A new reading mode based on balanced pre-charging and group decoding

Qin

Lin

et al. 2020

IEICE Electron. Express

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In this paper, the balanced pre-charging and group decoding are presented to realize in-memory computing which can achieve continuous read operations after only one pre-charge operation. Compared with the analog computing of multi-row parallel reading, this structure adopts digital domain computing, which improves the accuracy of computing; compared with the non multi-row in-memory computing, it improves the computation speed. The simulation results of noise margin, read times, and read speed show that the proposed method can improve memory performance. The maximum stability can be improved by 13.8%, the read speed can be improved by 75%, and the power consumption can be reduced by 11.58%. Besides, it can be widely used in a variety of memory structures. The proposed method is applied to the existing in-memory computing structures to verify the effectiveness.

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Artificial Neural Networks in Hardware

Zheng¹,

Mazumder²

2019

Learning in Energy‐Efficient Neuromorphic Computing

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An In-Memory VLSI Architecture for Convolutional Neural Networks

Cited by 55 publications

References 23 publications

IMAC: In-Memory Multi-Bit Multiplication and ACcumulation in 6T SRAM Array

IMAC: In-Memory Multi-Bit Multiplication and ACcumulation in 6T SRAM Array

A new reading mode based on balanced pre-charging and group decoding

Artificial Neural Networks in Hardware

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