An In-DRAM BIST for 16 Gb DDR4 DRAM in the 2nd 10-nm-Class DRAM Process

Park, Jaewon; Lee, Jae Hoon; Park, Sang-Kil; Chun, Ki Chul; Sohn, Kiwon; Kang, Sungho

doi:10.1109/access.2021.3061349

Cited by 9 publications

(8 citation statements)

References 28 publications

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“…The FPGA performance of the DQL-BSLFSR-FD method is likened to existing approaches. The proposed method's FPGA performance is compared with the memory BIST with optimized BISR for fault detection (FPGA-MBIST-OBISR-FD) [22], SRAM-based Physically Unclonable Function (PUF) with Hot Carrier Injection (HCI) for fault detection (FPGA-PUF-HCI-FD) [23], and the Essential Spare Pivoting (ESP) based Local Repair Most (LRM) (FPGA-ESP-LRM-FD) [27], respectively.…”

Section: Resultsmentioning

confidence: 99%

“…In 2021, Park et al [27] presented the BIST model to process post-package inspections (PPI) for attaining fault-free Dynamic Random Access Memory (DRAM). Here, the compact and higher test coverage structures for in-DRAM-BIST were considered for resolving the area issues when applied to commodity Dynamic Random Access Memory.…”

Section: Related Workmentioning

confidence: 99%

“…The simulation outcomes of the DQL-BSLFSR-FD method are compared with existing methods, such as Extreme Learning Machine-based Autoencoder for fault diagnosis (ELM-AE-FD) [26], and built-in self-test (BIST) model-based post package inspections (PPI) for fault diagnosis (BIST-PPI-FD) [27], respectively.…”

Section: Introductionmentioning

confidence: 99%

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Deep Q-Learning with Bit-Swapping-Based Linear Feedback Shift Register fostered Built-In Self-Test and Built-In Self-Repair for SRAM

Ahmed

Alnatheer

2022

Micromachines

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Including redundancy is popular and widely used in a fault-tolerant method for memories. Effective fault-tolerant methods are a demand of today’s large-size memories. Recently, system-on-chips (SOCs) have been developed in nanotechnology, with most of the chip area occupied by memories. Generally, memories in SOCs contain various sizes with poor accessibility. Thus, it is not easy to repair these memories with the conventional external equipment test method. For this reason, memory designers commonly use the redundancy method for replacing rows–columns with spare ones mainly to improve the yield of the memories. In this manuscript, the Deep Q-learning (DQL) with Bit-Swapping-based linear feedback shift register (BSLFSR) for Fault Detection (DQL-BSLFSR-FD) is proposed for Static Random Access Memory (SRAM). The proposed Deep Q-learning-based memory built-in self-test (MBIST) is used to check the memory array unit for faults. The faults are inserted into the memory using the Deep Q-learning fault injection process. The test patterns and faults injection are controlled during testing using different test cases. Subsequently, fault memory is repaired after inserting faults in the memory cell using the Bit-Swapping-based linear feedback shift register (BSLFSR) based Built-in Self-Repair (BISR) model. The BSLFSR model performs redundancy analysis that detects faulty cells, utilizing spare rows and columns instead of defective cells. The design and implementation of the proposed BIST and Built-in Self-Repair methods are developed on FPGA, and Verilog’s simulation is conducted. Therefore, the proposed DQL-BSLFSR-FD model simulation has attained 23.5%, 29.5% lower maximum operating frequency (minimum clock period), and 34.9%, 26.7% lower total power consumption than the existing approaches.

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Section: Resultsmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

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Deep Q-Learning with Bit-Swapping-Based Linear Feedback Shift Register fostered Built-In Self-Test and Built-In Self-Repair for SRAM

Ahmed

Alnatheer

2022

Micromachines

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“…However, achieving near 10 nmclass of DRAM device structures is expected to be very difficult. 2 The scaling of DRAM is limited by the ongoing increase in transistor leakage current caused by the reduction in cell size, resulting in reliability issues such as shortened retention time. Therefore, it is expected that 3D DRAM devices like 2T0C (Figure 1b) will be necessary.…”

Section: ■ Introductionmentioning

confidence: 99%

“…DRAM devices have been continuously scaled, and by the end of 2023, 12 nm-class devices will be fabricated in mass production. However, achieving near 10 nm-class of DRAM device structures is expected to be very difficult . The scaling of DRAM is limited by the ongoing increase in transistor leakage current caused by the reduction in cell size, resulting in reliability issues such as shortened retention time.…”

Section: Introductionmentioning

confidence: 99%

Review of Material Properties of Oxide Semiconductor Thin Films Grown by Atomic Layer Deposition for Next-Generation 3D Dynamic Random-Access Memory Devices

Choi,

Lim,

Shin

et al. 2024

Chem. Mater.

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Dynamic random-access memory (DRAM) devices are essential volatile memory components in most digital devices. With the increasing demand for further low-power and high-density devices, the planar structure of DRAM devices encountered a "memory wall", ushering in an era of 3D DRAM architecture. InGaZnO-based thin-film transistors (IGZO TFTs) have a very low off current (<10 −22 A/μm), representing a solution for new channel materials for next-generation 3D DRAM devices. IGZO TFTs are back-end-of-line (BEOL)compatible, enabling them to move the DRAM peripheral circuitry under the memory array and integrate stacked DRAM cells. IGZO thin films have been widely studied for next-generation flat panel display applications. However, most studies have employed sputtering and solution-based systems, which hinder process compatibility in 3D DRAM devices with complex structures. Atomic layer deposition (ALD) is a viable alternative for solving these challenges. In this paper, we comprehensively review the reported Zn-, In-, Sn-, and Ga-based oxide semiconductors in terms of the ALD process (precursors, reactants, growth temperature, etc.), together with material properties such as purity, crystallinity, and electrical properties.

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Extremely high selective Si1−xGex-film wet etchant generating highly dissolved oxygen via peracetic acid oxidant for lateral gate-all-around FETs with a logic node of less than 3-nm

Lee,

Lee

et al. 2023

Chemical Engineering Journal

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An In-DRAM BIST for 16 Gb DDR4 DRAM in the 2nd 10-nm-Class DRAM Process

Cited by 9 publications

References 28 publications

Deep Q-Learning with Bit-Swapping-Based Linear Feedback Shift Register fostered Built-In Self-Test and Built-In Self-Repair for SRAM

Deep Q-Learning with Bit-Swapping-Based Linear Feedback Shift Register fostered Built-In Self-Test and Built-In Self-Repair for SRAM

Review of Material Properties of Oxide Semiconductor Thin Films Grown by Atomic Layer Deposition for Next-Generation 3D Dynamic Random-Access Memory Devices

Extremely high selective Si1−xGex-film wet etchant generating highly dissolved oxygen via peracetic acid oxidant for lateral gate-all-around FETs with a logic node of less than 3-nm

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