An improved low-voltage low-power CMOS comparator to be used in high-speed pipeline ADCs

Amaral, P.; Goes, J.; Paulino, Nuno; Steiger-Garção, Adolfo

doi:10.1109/iscas.2002.1010660

Cited by 28 publications

(9 citation statements)

References 11 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The designing of comparators [5] has decisive impact on the overall performance of high speed analog to digital converters. The comparator architecture adopted in this 7-bit flash ADC comprises of a preamplifier stage [10] followed by a dynamic latched comparator structure.…”

Section: B Comparatormentioning

confidence: 99%

A 7-bit 500-MHz flash ADC

Jayakumar

Vishnu

2014

2014 First International Conference on Computational Systems and Communications (ICCSC)

View full text Add to dashboard Cite

This paper describes the systematic design of a high speed and high resolution CMOS Flash Analog-To-Digital Converter. A 7-bit flash ADC is implemented in cadence environment using gpdk90-nm CMOS technology with a 1.2-V analog supply voltage. The converter achieves a signal-to-(noise + distortion) ratio of 39.3574dB and signal-to-spurious-free-dynamic-range of 40.7547dB with a sampling rate of 500MHz.

show abstract

Section: B Comparatormentioning

confidence: 99%

A 7-bit 500-MHz flash ADC

Jayakumar

Vishnu

2014

2014 First International Conference on Computational Systems and Communications (ICCSC)

View full text Add to dashboard Cite

show abstract

“…This approach uses a dynamic latch, contrary to a static latch, in order to reduce the current consumption in the static regime (Amaral 2002). Figure 3 shows the circuit topology of the clocked comparator.…”

Section: Clocked Comparator Circuitmentioning

confidence: 99%

“…This arrangement consists in placing several stages in cascade of low bit resolution per stage, and thus very fast. Typically this resolution is 1.5 or 2.5 bit/stage (Amaral 2002).…”

Section: Introductionmentioning

confidence: 99%

High-speed low-power CMOS comparator dedicated to 10 bit 20 MHz pipeline ADCs for RF WLAN applications

Guermaz

Bouzerara

Belaroussi

et al. 2008

International Journal of Electronics

View full text Add to dashboard Cite

This article describes and analyses a low power and high speed comparator. The designed comparator is intended to be implemented in a 10 bit 20 MHz Pipeline Analogue-to-Digital Converter dedicated to RF Wireless Local Area Network (WLAN) applications. This comparator is based on the switched capacitor network using a two-phase non-overlapping clock. The offset voltage of the designed comparator has been reduced by means of an active positive feedback. The analyses and simulation results which have been obtained using 0.8 mm CMOS AMS process parameters, with a power supply voltage of 5 V and an input common mode of 2-3 V, show that this comparator exhibits a propagation delay of 17.3 ns, an offset voltage of about 77.3 mV, a good accuracy and a low power consumption of about 0.8 mW. The predicted performance is verified by analyses and simulations using PSPICE tool.

show abstract

“…During the regeneration phase, the input nodes can be isolated from the regeneration nodes using switches [3]. Furthermore, isolation between the drains of differential pair transistors and the regeneration nodes reduces kickback noise [4], [5]. However, input voltage is still disturbed when the sampling switches close and makes the input transistors go into the triode region easily; therefore the drain voltage variations will originate kickback noise in evidence.…”

Section: Introductionmentioning

confidence: 99%

A 1.2V 246uW CMOS latched comparator with neutralization technique for reducing Kickback Noise

Fahmy

Pokharel

Kanaya

et al. 2010

TENCON 2010 - 2010 IEEE Region 10 Conference

View full text Add to dashboard Cite

A low power CMOS latched comparator has been designed in TSMC 0.18µm employ neutralization technique for reducing Kickback Noise. The simulation results demonstrate that it can work at 1GHz suitable for high speed applications. Measurement results prove that the latched comparator consumes 246µW with a power supply of 1.2v at 10MHz. A simulation method for accurately determining dynamic offset in latched comparator is presented.

show abstract

An improved low-voltage low-power CMOS comparator to be used in high-speed pipeline ADCs

Cited by 28 publications

References 11 publications

A 7-bit 500-MHz flash ADC

A 7-bit 500-MHz flash ADC

High-speed low-power CMOS comparator dedicated to 10 bit 20 MHz pipeline ADCs for RF WLAN applications

A 1.2V 246uW CMOS latched comparator with neutralization technique for reducing Kickback Noise

Contact Info

Product

Resources

About