An Improved Hardware Implementation of the Grain-128a Stream Cipher

Mansouri, Shohreh Sharif; Dubrova, Elena

doi:10.1007/978-3-642-37682-5_20

Cited by 5 publications

(4 citation statements)

References 8 publications

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“…Since g n−1 in the Fibonacci confguration of Grain-128AEADv2 can be the same as that of Grain-128a and that of Grain-128AEAD, the Galois transformation of Grain-128AEADv2 can be identical to that of Grain-128a and that of Grain-128AEAD. Details about the feedback functions after the Galois transformation of Grain-128a can be seen in [7]. According to [7], the Galois transformation of Grain-128AEADv2 cannot be applied when the parallel level of the hardware implementation of Grain-128AEADv2 is above 16.…”

Section: Te Galois Transformation Versionmentioning

confidence: 99%

“…Details about the feedback functions after the Galois transformation of Grain-128a can be seen in [7]. According to [7], the Galois transformation of Grain-128AEADv2 cannot be applied when the parallel level of the hardware implementation of Grain-128AEADv2 is above 16.…”

Section: Te Galois Transformation Versionmentioning

confidence: 99%

“…In fact, there have been several hardware implementations of the Grain family. In [7], the hardware implementation of Grain-128a was proposed. In [8], the efcient hardware implementation of Grain-128AEAD was proposed.…”

Section: Introductionmentioning

confidence: 99%

“…Tus, it will not infuence the generality of the hardware implementation of Grain-128AEADv2. Second, since the feedback functions are not changed, the parallel level of the hardware implementation of Grain-128AEADv2 with the pipeline-like pre-computation technique can be up to x32, which can be two times the maximum parallel level (x16) reached by the hardware implementation of Grain-128AEADv2 with the Galois transformation [7]. As the throughput-area ratio of a hardware implementation increases with its parallel level, it can achieve an efcient hardware implementation of Grain-128AEADv2.…”

Section: Introductionmentioning

confidence: 99%

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Efficient (Masked) Hardware Implementation of Grain-128AEADv2

Zhang

Lin

2023

Security and Communication Networks

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We consider the efficient hardware implementation of Grain-128AEADv2, which is the second version of Grain-128AEAD (one of the lightweight cryptography finalist candidates). In order to counteract side-channel attacks, the efficient masked hardware implementation of Grain-128AEADv2 is also considered under the idea of domain-oriented masking. In detail, the so-called pipeline-like pre-computation technique is applied to increase the throughput-area ratio of the (masked) hardware implementation of Grain-128AEADv2. The performance of the (masked) hardware implementation of Grain-128AEADv2 is evaluated on ASIC and FPGA. For the unmasked version, the highest throughput-area ratio can be 2.14 M b p s / G E on ASIC and 9.34 M b p s / S l i c e on FPGA. For the masked version, the highest throughput-area ratio can be 0.37 M b p s / G E on ASIC and 1.72 M b p s / S l i c e on FPGA. Then, the security of the masked hardware implementation of Grain-128AEADv2 is verified with the simulated T-Test. To the best of our knowledge, this is the first published work about the (masked) hardware implementation of Grain-128AEADv2. In light of this, this contribution may help researchers and practitioners to accurately compare the efficiency and the security of the hardware implementation of Grain-128AEADv2 with those of other lightweight cryptography algorithms.

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Section: Te Galois Transformation Versionmentioning

confidence: 99%

Section: Te Galois Transformation Versionmentioning

confidence: 99%