Efficient Hardware Implementations of Grain-128AEAD

Sönnerup, Jonathan; Hell, Martin; Sönnerup, Mattias; Khattar, Ripudaman

doi:10.1007/978-3-030-35423-7_25

Cited by 7 publications

(5 citation statements)

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“…For a given parallel level p, the highest throughput-area ratio of a hardware implementation can be related to the highest frequency that can be achieved, while the highest frequency of a hardware implementation depends on the critical path which corresponds to the maximal delay of two fip-fops. Similar to [8], the potential critical paths of Grain-128AEADv2 should be in the following ones: Although there are several potential critical paths, some can be excluded by analyzing the update functions of Grain-128AEADv2. Te update functions of the NFSR and the LFSR in the initialization phase can be more complicated than those in the generation phase because y needs to be additionally XORed to f and g. Ten, D n and D y can be FF FF excluded because of the existence of D yn .…”

Section: Te Straightforward Versionmentioning

confidence: 99%

“…Since only one of the generated bits is used for authentication, the update of the accumulator A with (9) can hold for the parallel level p ≤ 2. However, for the parallel level p ≥ 4, A can be updated as [8]…”

Section: Pipelining the Accumulatormentioning

confidence: 99%

“…In order to make D ya shorter, Sönnerup et al [8] inserted a pipeline step between y and A and isolated A. However, in the Galois transformation version and the pipeline-like pre-computation version, we insert the pipeline step in the update of A for the parallel level p ≥ 16 as shown in Figure 4.…”

Section: Pipelining the Accumulatormentioning

confidence: 99%

“…In [7], the hardware implementation of Grain-128a was proposed. In [8], the efcient hardware implementation of Grain-128AEAD was proposed. In order to increase the throughput-area ratio, the Galois transformation of the NFSR was adopted in these hardware implementations.…”

Section: Introductionmentioning

confidence: 99%

“…One strategy to increase the throughput-area ratio of the hardware implementation of Grain-128AEADv2 is to apply the pipeline technique, which aims to increase the frequency of the hardware implementation of Grain-128AEADv2 by inserting registers into the critical path. However, it is not possible to apply the pipeline technique for FSRs due to their intrinsic feedback property [8]. In light of this, a pipeline-like pre-computation technique is proposed.…”

Section: Introductionmentioning

confidence: 99%

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Efficient (Masked) Hardware Implementation of Grain-128AEADv2

Zhang

Lin

2023

Security and Communication Networks

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We consider the efficient hardware implementation of Grain-128AEADv2, which is the second version of Grain-128AEAD (one of the lightweight cryptography finalist candidates). In order to counteract side-channel attacks, the efficient masked hardware implementation of Grain-128AEADv2 is also considered under the idea of domain-oriented masking. In detail, the so-called pipeline-like pre-computation technique is applied to increase the throughput-area ratio of the (masked) hardware implementation of Grain-128AEADv2. The performance of the (masked) hardware implementation of Grain-128AEADv2 is evaluated on ASIC and FPGA. For the unmasked version, the highest throughput-area ratio can be 2.14 M b p s / G E on ASIC and 9.34 M b p s / S l i c e on FPGA. For the masked version, the highest throughput-area ratio can be 0.37 M b p s / G E on ASIC and 1.72 M b p s / S l i c e on FPGA. Then, the security of the masked hardware implementation of Grain-128AEADv2 is verified with the simulated T-Test. To the best of our knowledge, this is the first published work about the (masked) hardware implementation of Grain-128AEADv2. In light of this, this contribution may help researchers and practitioners to accurately compare the efficiency and the security of the hardware implementation of Grain-128AEADv2 with those of other lightweight cryptography algorithms.

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Section: Te Straightforward Versionmentioning

confidence: 99%

Section: Pipelining the Accumulatormentioning

confidence: 99%

Section: Pipelining the Accumulatormentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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