An improved frequency compensation technique for CMOS operational amplifiers

Ahuja, B.K.

doi:10.1109/jssc.1983.1052012

Cited by 450 publications

(140 citation statements)

References 6 publications

Supporting

Mentioning

137

Contrasting

Unclassified

Order By: Relevance

“…5(b) is folded cascode type. Due to its high gain characteristics, the frequency compensation and CMFB (Common Mode Feedback) circuit is added [10]. In order to alleviate the common mode oscillation due to the CMFB, the gain of op-amp and current of CMFB are optimized.…”

Section: Programmable Gain Amplifier Of Transmittermentioning

confidence: 99%

A 67.5 dB SFDR Full-CMOS VDSL2 CPE Transmitter and Receiver with Multi-Band Low-Pass Filter

Park¹,

Park²,

Pu³

et al. 2010

JSTS:Journal of Semiconductor Technology and Science

View full text Add to dashboard Cite

Abstract-This paper presents a full-CMOS transmitter and receiver for VDSL2 systems. The transmitter part consists of the low-pass filter, programmable gain amplifier (PGA) and 14-bit DAC. The receiver part consists of the low-pass filter, variable gain amplifier (VGA), and 13-bit ADC. The low pass filter and PGA are designed to support the variable data rate. The RC bank sharing architecture for the low pass filter has reduced the chip size significantly. And, the 80 Msps, high resolution DAC and ADC are integrated to guarantee the SNR. Also, the transmitter and receiver are designed to have a wide dynamic range and gain control range because the signal from the VDSL2 line is variable depending on the distance. The chip is implemented in 0.25 m CMOS technology and the die area is 5 mm × 5 mm. The spurious free dynamic range (SFDR) and SNR of the transmitter and receiver are 67.5 dB and 41 dB, respectively. The power consumption of the transmitter and receiver are 160 mW and 250 mW from the supply voltage of 2.5 V, respectively.

show abstract

Section: Programmable Gain Amplifier Of Transmittermentioning

confidence: 99%

A 67.5 dB SFDR Full-CMOS VDSL2 CPE Transmitter and Receiver with Multi-Band Low-Pass Filter

Park¹,

Park²,

Pu³

et al. 2010

JSTS:Journal of Semiconductor Technology and Science

View full text Add to dashboard Cite

show abstract

“…The class of compensation in which the compensation current is fed back indirectly from the output to the internal high impedance node is defined as Indirect Feedback Frequency Compensation [1], [3], [4]. In this method, the compensation capacitor is connected to an internal low impedance node in the first gain stage, which allows indirect feedback of the compensation current from the output node to the internal high-impedance node i.e.…”

Section: Low Voltage Indirect Feedback Compensationmentioning

confidence: 99%

Indirect compensation techniques for three-stage CMOS op-amps

Saxena¹,

Baker²

2009

2009 52nd IEEE International Midwest Symposium on Circuits and Systems

View full text Add to dashboard Cite

“…When there are cascode nodes in the first stage, cascode compensation, in which the compensation capacitor is connected to the cascode node instead of the first stage output, can be used instead of the standard Miller compensation [175,176]. It offers higher GBW and the RHP zero is at a much higher frequency.…”

Section: Frequency Compensationmentioning

confidence: 99%

Circuit Techniques for Low-Voltage and High-Speed A/D Converters

Waltari¹,

Halonen²

2003

The International Series in Engineering and Computer Science

View full text Add to dashboard Cite

The increasing digitalization in all spheres of electronics applications, from telecommunications systems to consumer electronics appliances, requires analog-to-digital converters (ADCs) with a higher sampling rate, higher resolution, and lower power consumption. The evolution of integrated circuit technologies partially helps in meeting these requirements by providing faster devices and allowing for the realization of more complex functions in a given silicon area, but simultaneously it brings new challenges, the most important of which is the decreasing supply voltage.Based on the switched capacitor (SC) technique, the pipelined architecture has most successfully exploited the features of CMOS technology in realizing high-speed high-resolution ADCs. An analysis of the effects of the supply voltage and technology scaling on SC circuits is carried out, and it shows that benefits can be expected at least for the next few technology generations. The operational amplifier is a central building block in SC circuits, and thus a comparison of the topologies and their low voltage capabilities is presented.It is well-known that the SC technique in its standard form is not suitable for very low supply voltages, mainly because of insufficient switch control voltage. Two low-voltage modifications are investigated: switch bootstrapping and the switched opamp (SO) technique. Improved circuit structures are proposed for both. Two ADC prototypes using the SO technique are presented, while bootstrapped switches are utilized in three other prototypes.An integral part of an ADC is the front-end sample-and-hold (S/H) circuit. At high signal frequencies its linearity is predominantly determined by the switches utilized. A review of S/H architectures is presented, and switch linearization by means of bootstrapping is studied and applied to two of the prototypes. Another important parameter is sampling clock jitter, which is analyzed and then minimized with carefully-designed clock generation and buffering.The throughput of ADCs can be increased by using parallelism. This is demonii strated on the circuit level with the double-sampling technique, which is applied to S/H circuits and a pipelined ADC. An analysis of nonidealities in double-sampling is presented. At the system level parallelism is utilized in a time-interleaved ADC. The mismatch of parallel signal paths produces errors, for the elimination of which a timing skew insensitive sampling circuit and a digital offset calibration are developed. A total of seven prototypes are presented: two double-sampled S/H circuits, a time-interleaved ADC, an IF-sampling self-calibrated pipelined ADC, a current steering DAC with a deglitcher, and two pipelined ADCs employing the SO technique.

show abstract

An improved frequency compensation technique for CMOS operational amplifiers

Cited by 450 publications

References 6 publications

A 67.5 dB SFDR Full-CMOS VDSL2 CPE Transmitter and Receiver with Multi-Band Low-Pass Filter

A 67.5 dB SFDR Full-CMOS VDSL2 CPE Transmitter and Receiver with Multi-Band Low-Pass Filter

Indirect compensation techniques for three-stage CMOS op-amps

Circuit Techniques for Low-Voltage and High-Speed A/D Converters

Contact Info

Product

Resources

About