An Improved DCM-Based Tunable True Random Number Generator for Xilinx FPGA

Johnson, Anju P.; Chakraborty, Rajat Subhra; Mukhopadyay, Debdeep

doi:10.1109/tcsii.2016.2566262

Cited by 76 publications

(47 citation statements)

References 4 publications

(11 reference statements)

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“…This shows that the neuron fires more regular as its input frequency increases. This is straight forward and finds explanation from jittery behaviour of Xilinx DCM module [16] and also LIF neuron model.…”

Section: Statistical Comparisonmentioning

confidence: 92%

Homeostatic fault tolerance in spiking neural networks utilizing dynamic partial reconfiguration of FPGAs

Johnson

Liu

Millard

et al. 2017

2017 International Conference on Field Programmable Technology (ICFPT)

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We present a novel methodology that addresses the problem of faults in synapses of a spiking neural network using astrocyte regulation, inspired by recovery processes in the brain. Since Field Programmable Gate Arrays (FPGAs) are widely used for neural network applications, we aim to achieve fault tolerance in an astrocyte-neuron unit implemented on an FPGA. A fault is considered as a reduction in transmission probability of a synapse, leading to reduced spiking activity. Our novel repair mechanism exploits Dynamic Partial Reconfiguration (DPR) of the FPGA Clock Management Tiles (CMTs) to increase the clock frequency of neurons with reduced synaptic input, which restores the firing rate to pre-fault levels. We demonstrate the repair methodology on a spiking neural network implemented on an FPGA. The system maintains effective functional behavior with a loss of up to 99% of the original synaptic inputs to a neuron. Our repair mechanism has minimal hardware overhead with the tuning circuit (repair unit) which consumes only 0.8215% of the complete design and therefore supports scalable implementations. Additionally, the overall architecture has a minimal impact on power consumption (1.371W ). The work opens up a novel way to utilize the capabilities of modern hardware to mimic homeostatic self-repair behavior achieving fault recovery.

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Section: Statistical Comparisonmentioning

confidence: 92%

Homeostatic fault tolerance in spiking neural networks utilizing dynamic partial reconfiguration of FPGAs

Johnson

Liu

Millard

et al. 2017

2017 International Conference on Field Programmable Technology (ICFPT)

Self Cite

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“…A ring oscillator is a device composed of odd number of NOT gate in a closed loop whose output oscillates between two voltage level, representing TRUE or FALSE [3]. Jitter in oscillators are used as the source of randomness [5].…”

Section: Ring Oscillatormentioning

confidence: 99%

“…In the proposed system random number generator uses only two flip-flops and two 4 input look-up table for every random sequence that is generated. This design is implemented on a Xilinx FPGA [1,3] board so this system is assured to be a more secure because there is no need of external components. In this paper the 32-bit true random number is generated at a frequency of 125 MHz with a bit rate of 4 Gbps.…”

Section: Hardware Random Number Generation Using Generalized Ro and Lhcamentioning

confidence: 99%

Hardware Random Number GeneratorUsing FPGA

Devi

Chithra

Sethumadhavan

2019

JCSM

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Random numbers are employed in wide range of cryptographic applications. Output of an asynchronous sampling of ring oscillators can be used as the source of randomness and Linear Hybrid Cellular Automata is used to improve the quality of random data. FPGA is an ideal platform for the implementation of random number generator for cryptographic applications. The circuit described in this paper has been implemented on a highly efficient FPGA board which generated a 32-bit random number at a frequency of 125 MHz. The generated sequence of random numbers were subjected to Diehard test and NIST test for testing randomness and found to pass these tests. These tests are a battery of statistical tests for measuring the quality of a random number generator.

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“…Field programmable gate array-based applications provide high-speed implementation and reconfigurable design process. In cryptographic applications, FPGAs occupy an important place [28][29][30][31][32][33][34][35]. The proposed design in the third scenario is run on Virtex II Pro XC2VP30 FPGA development board by using Verilog HDL as the source type.…”

Section: Field Programmable Gate Array Implementation Of Chaotic Cellmentioning

confidence: 99%

Chaotic cellular neural network‐based true random number generator

Karakaya

Çelik

Gülten

2017

Circuit Theory & Apps

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Summary This paper presents implementation of a chaotic cellular neural network (CNN)‐based true random number generator on a field programmable gate array (FPGA) board. In this implementation, discrete time model of the chaotic CNN is used as the entropy source. Random number series are generated for three scenarios. Obtained number series are tested by using NIST 800.22 statistical test suite. Also, the scale index technique is carried out for these three scenarios to determine the degree of non‐periodicity for key stream. Copyright © 2017 John Wiley & Sons, Ltd.

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An Improved DCM-Based Tunable True Random Number Generator for Xilinx FPGA

Cited by 76 publications

References 4 publications

Homeostatic fault tolerance in spiking neural networks utilizing dynamic partial reconfiguration of FPGAs

Homeostatic fault tolerance in spiking neural networks utilizing dynamic partial reconfiguration of FPGAs

Hardware Random Number GeneratorUsing FPGA

Chaotic cellular neural network‐based true random number generator

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