An implementation technique of dynamic CMOS circuit applicable to asynchronous/synchronous logic

Yoshizawa, Hiroyasu; Taniguchi, K.; Nakashi, Kenichi

doi:10.1109/iscas.1998.706862

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B Phase Detector With Charge Pump1

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Cited by 5 publications

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“…4 shows a block diagram of the phase detector. It contains two TSPC flip-flops [7], two inverters and a NOR gate. The reference signal and the feedback signal are connected to the reset port of each flip-flop.…”

Section: B Phase Detector With Charge Pumpmentioning

confidence: 99%

Integer-N phase locked loop for bluetooth receiver in CMOS 130 nm technology

Butryn

Siwiec

Kopanski

et al. 2016

2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits &Amp; Systems (DDECS)

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The paper presents an Integer-N phase locked loop (PLL) for Bluetooth receiver implemented in CMOS 130 nm technology. The presented phase locked loop consists of an LC quadrature voltage controlled oscillator with capacitor bank, a tri-state phase-frequency detector with charge pump, a third order passive filter and a programmable divider. The PLL has a supply voltage of 1.2 V and dissipates 2.4 mW. The output frequency range of the phase locked loop is from 2.2 GHz to 2.8 GHz and phase noise is equal -124 dBm/Hz at 3 MHz from carrier frequency.

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Section: B Phase Detector With Charge Pumpmentioning

confidence: 99%