An Implementation of Performance-Driven Block and I/O Placement for Chip-Package Codesign

Lai, Ming-Fang; Chen, Hung-Ming

doi:10.1109/isqed.2008.4479806

Cited by 12 publications

(6 citation statements)

References 10 publications

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“…The aforementioned studies provide RDL routing techniques for flip-chip designs, and some of them consider the chip-package [8,18,19,22,37] or even chip-package-board codesign [13]. On the other hand, not much work discusses the RDL routing techniques for advanced packages [20,26], and even none considers the horizontal or vertical integration issues for advanced packages such as InFO packages.…”

Section: Physical Designmentioning

confidence: 99%

Intelligent design automation for 2.5/3D heterogeneous SoC integration

Jiang

Chang

Huang

et al. 2020

Proceedings of the 39th International Conference on Computer-Aided Design

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Section: Physical Designmentioning

confidence: 99%

Intelligent design automation for 2.5/3D heterogeneous SoC integration

Jiang

Chang

Huang

et al. 2020

Proceedings of the 39th International Conference on Computer-Aided Design

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“…To improve the layout performance or to speed up design cycle, several previous works proposed cross-domain co-design methodology in various aspects such as placement [4,5], routing [6,7,8], assignment [9,10,11] and design flow [12,13]. For chip-package co-design problem, [4] proposed a multi-step algorithm based upon integer linear programming to find an I/O placement solution satisfying all design constraints.…”

Section: A Previous Workmentioning

confidence: 99%

“…For chip-package co-design problem, [4] proposed a multi-step algorithm based upon integer linear programming to find an I/O placement solution satisfying all design constraints. [5] addressed a block and I/O buffer placement method that optimizes wire length and signal skew. Some researches [6,7] developed RDL routers for area-I/O to achieve better performance.…”

Section: A Previous Workmentioning

confidence: 99%

Routability-driven bump assignment for chip-package co-design

Chen

Tsai

Chen

et al. 2014

2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC)

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In current chip and package designs, it is a bottleneck to simultaneously optimize both pin assignment and pin routing for different design domains (chip, package, and board). Usually the whole process costs a huge manual effort and multiple iterations thus reducing profit margin. Therefore, we propose a fast heuristic chip-package co-design algorithm in order to automatically obtain a bump assignment which introduces high routability both in RDL routing and substrate routing (100% in our real case). Experimental results show that the proposed method (inspired by board escape routing algorithms) automatically finishes bump assignment, RDL routing and substrate routing in a short time, while the traditional co-design flow requires weeks even months.

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“…The inter-chip connections of this result are shorter and simpler than that in Figure 2 consume fewer layers and vias in a standard interposer and thus improve its signal quality and reduce the manufacturing cost. Many previous works have addressed various codesign problems as follows: (1) chip-package codesign [5,6,13,17,18,21,23], (2) package-board codesign [8,16], and (3) chip-packageboard codesign [7,15,20]. However, no previous work is focused on silicon interposers, key components of interposer-based 3D ICs.…”

Section: Introductionmentioning

confidence: 99%

“…Xiong et al [23] defined some constraints for chip-package codesign and proposed an effective multi-step algorithm to solve a constraint-driven I/O placement problem. In addition, some previous works focused on the signal skew between chips and packages [6,13,18,21]. For package-board codesign, Fang et al [8] used Delaunay triangulation and Voronoi diagrams to create triangular tile models and then route signal nets with the models.…”

Section: Introductionmentioning

confidence: 99%

Multiple chip planning for chip-interposer codesign

Chang

2013

Proceedings of the 50th Annual Design Automation Conference

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An interposer-based three-dimensional integrated circuit, which introduces a silicon interposer as an interface between chips and a package, is one of the most promising integration technologies for modern and next-generation circuit designs. Inter-chip connections can be routed on the interposer by chip-scale wires to enhance design quality. However, its design complexity increases dramatically due to the extra interposer interface. Consequently, it is desirable to simultaneously consider the co-design of the interposer and multiple chips mounted on it. This paper addresses the first work of chip-interposer codesign to place multiple chips on an interposer to reduce inter-chip wirelength. For this problem, we propose a new hierarchical B*-tree to simultaneously place multiple chips, macros, and I/O Buffers. An approach based on bipartite matching is then proposed to concurrently assign signals from I/O buffers to micro bumps. Experimental results show that our approach is effective and efficient for the codesign problem.

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An Implementation of Performance-Driven Block and I/O Placement for Chip-Package Codesign

Cited by 12 publications

References 10 publications

Intelligent design automation for 2.5/3D heterogeneous SoC integration

Intelligent design automation for 2.5/3D heterogeneous SoC integration

Routability-driven bump assignment for chip-package co-design

Multiple chip planning for chip-interposer codesign

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