An implementation of branch target buffer for high performance applications

Il, Sonh， Seung; Yang, Hoon Mo; Lee, Moon Key

doi:10.1109/tencon.1995.496448

Cited by 3 publications

(4 citation statements)

References 1 publication

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“…Conversely, the authors in [3] have coupled the predictor with the BTB structure by storing two history information bits to dynamically predict the branch path, in addition to the branch tag and target address. As such, the predicted branch direction can be obtained in the fetch stage.…”

Section: Related Workmentioning

confidence: 99%

Implementation of branch delay in Superscalar processors by reducing branch penalties

Khanna

Verma²,

Biswas

et al. 2010

2010 IEEE 2nd International Advance Computing Conference (IACC)

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Branch prediction is crucial to maintaining high performance in modern Superscalar processor. Today's Superscalar processors achieve high performance by executing multiple independent instructions in parallel. One of the most impedement to the performance of wide-issue superscalar processor is the presence of conditional branches. Conditional branches can occur as frequently as one in every 5 or 6 instructions, leading to heavy misprediction penalties in superscalar architectures. Ideal speed-up in superscalar processor is seldom achieved due to stalls and breaks in the execution stream. These interrupts are caused by data and control hazards which deteroits the superscalar processor performance. Branch target buffer (BTB) can reduces the performance penalty of branches in superscalar processor by predicting the path of the branch and caching information used by the branch. No stalls will be encountered if the branch entry is found in the BTB and prediction is correct. Otherwise, the penalty will be of atleast '2' cycles. This paper proposes an algorithm for superscalar processor based on changing the BTB structure to eliminate the misprediction penalty. It also highlights a problem in the previous BTB algorithm (nested branches problem) and proposes a solution to it.

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Section: Related Workmentioning

confidence: 99%

Implementation of branch delay in Superscalar processors by reducing branch penalties

Khanna

Verma²,

Biswas

et al. 2010

2010 IEEE 2nd International Advance Computing Conference (IACC)

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show abstract

“…In that case, a separate predictor is used in decode stage; it gives the decision for the branch direction by the help of the prediction information stored in BTB. Conversely, the authors in [3] have coupled the predictor with the BTB structure by storing two history information bits to dynamically predict the branch path, in addition to the branch tag and target address. As such, the predicted branch direction can be obtained in the fetch stage.…”

Section: Related Workmentioning

confidence: 99%

“…Two methods are usually used: one is to save branches on their first execution and the second is to save branches on their first taken execution [3]. In [1], the first choice is adopted where only the taken instructions are saved.…”

Section: Related Workmentioning

confidence: 99%

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Reducing misprediction penalty in the Branch Target Buffer

Abdelhak

Sil

Wang

et al. 2007

2007 50th Midwest Symposium on Circuits and Systems

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Ideal speedup in pipelined processors is seldom achieved due to stalls and breaks in the execution stream. These interrupts are caused by data and control hazards, the latter, however, can be the most detrimental to pipeline performance. Branch Target Buffer (BTB) can reduce performance penalty of branches in pipelined processors by predicting the path of the branch and caching information used by the branch. No stalls will be encountered if the branch entry is found in BTB and the prediction is correct; otherwise, the penalty will be at least two cycles. This paper proposes a novel algorithm based on changing the BTB structure to eliminate the branch misprediction penalty. It also highlights a problem in the previous BTB algorithms (nested branches problem) and proposes a solution to it.

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A Low Power Branch Prediction for Deep Learning on RISC-V Processor

Sun

Chen

et al. 2021

2021 IEEE 32nd International Conference on Application-Specific Systems, Architectures and Processors (ASAP)

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An implementation of branch target buffer for high performance applications

Cited by 3 publications

References 1 publication

Implementation of branch delay in Superscalar processors by reducing branch penalties

Implementation of branch delay in Superscalar processors by reducing branch penalties

Reducing misprediction penalty in the Branch Target Buffer

A Low Power Branch Prediction for Deep Learning on RISC-V Processor

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