An Implementation of an SHA-3 Hash Function Validation Program and Hash Algorithm on 16bit-UICC

Lee, Hee-Woong; Hong, Dowon; Kim, Hyunil; Seo, Changho; Park, Kishik

doi:10.5626/jok.2014.41.11.885

Cited by 3 publications

(4 citation statements)

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“…It is widely known that the hardware implementation of SHA-3 has the advantage of faster execution than that of SHA-1 and SHA-2 [32]. However, with respect to software implementation, SHA-3 is much slower than existing hash algorithm including SHA-2 [13][14][15][16][17]. Currently, existing SHA-3 software on a variety of IoT devices, including 8-bit AVR MCUs, are implemented according to the pseudo-codes of the NIST SHA-3 standard [13][14][15][16].…”

Section: Overview Of 8-bit Avr Mcusmentioning

confidence: 99%

“…However, with respect to software implementation, SHA-3 is much slower than existing hash algorithm including SHA-2 [13][14][15][16][17]. Currently, existing SHA-3 software on a variety of IoT devices, including 8-bit AVR MCUs, are implemented according to the pseudo-codes of the NIST SHA-3 standard [13][14][15][16]. The existing implementations following the pseudo-codes of the standard compute π and ρ in the combined way as π ∼ ρ rather than computing them separately, because rotate-operation (ρ) can be embedded in the process of π computation.…”

Section: Overview Of 8-bit Avr Mcusmentioning

confidence: 99%

“…Through lines 2-9 in Algorithm 3, load one lane to R8-R15 registers and return the address value of the X register through lines 10 and 11. Similar to line 1, line 12 adds offset value to the X register to determine the i value of D[i, z] and then lines [13][14][15][16][17][18][19][20][21][22][23][24][25][26][27]…”

Section: Proposed Assembly Code On 8-bit Avr Mcusmentioning

confidence: 99%

“…Until now, researchers had examined the security of SHA-3 (Keccak). While SHA-3 is proven to be secure against known attacks, its usage is limited due to its inefficiency [13][14][15][16][17][18][19][20]. It is known that SHA-3 is three times slower than SHA-256 in the 8-bit AVR platform [12,[15][16][17] and two times slower than SHA-512 in a CPU environment [2,[18][19][20].…”

Section: Introductionmentioning

confidence: 99%

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Chaining Optimization Methodology: A New SHA-3 Implementation on Low-End Microcontrollers

2021

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Since the Keccak algorithm was selected by the US National Institute of Standards and Technology (NIST) as the standard SHA-3 hash algorithm for replacing the currently used SHA-2 algorithm in 2015, various optimization methods have been studied in parallel and hardware environments. However, in a software environment, the SHA-3 algorithm is much slower than the existing SHA-2 family; therefore, the use of the SHA-3 algorithm is low in a limited environment using embedded devices such as a Wireless Sensor Networks (WSN) enviornment. In this article, we propose a software optimization method that can be used generally to break through the speed limit of SHA-3. We combine the θ, π, and ρ processes into one, reducing memory access to the internal state more efficiently than conventional software methods. In addition, we present a new SHA-3 implementation for the proposed method in the most constrained environment, the 8-bit AVR microcontroller. This new implementation method, which we call the chaining optimization methodology, implicitly performs the π process of the f-function while minimizing memory access to the internal state of SHA-3. Through this, it achieves up to 26.1% performance improvement compared to the previous implementation in an AVR microcontroller and reduces the performance gap with the SHA-2 family to the maximum. Finally, we apply our SHA-3 implementation in Hash_Deterministic Random Bit Generator (Hash_DRBG), one of the upper algorithms of a hash function, to prove the applicability of our chaining optimization methodology on 8-bit AVR MCUs.

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Section: Overview Of 8-bit Avr Mcusmentioning

confidence: 99%

Section: Overview Of 8-bit Avr Mcusmentioning

confidence: 99%

Section: Proposed Assembly Code On 8-bit Avr Mcusmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Chaining Optimization Methodology: A New SHA-3 Implementation on Low-End Microcontrollers

2021

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Implementation of SHA-3 Algorithm Based On ARM-11 Processors

Kang¹,

Lee²,

Hong

et al. 2015

Journal of the Korea Institute of Information Security and Cryp

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As the smart era, the use of smart devices is increasing. Smart devices are widely used to provide a human convenience, but there is a risk that information is exposed. The smart devices to prevent this problem includes the encryption algorithm. Among them, The hash function is an encryption algorithm that is used essentially to carry out the algorithm, such as data integrity, authentication, signature. As the issue raised in the collision resistance of SHA-1 has recently been causing a safety problem, and SHA-1 hash function based on the current standard of SHA-2 would also be a problem in the near future safety. Accordingly, NIST selected KECCAK algorithm as SHA-3, it has become necessary to implement this in various environments for this algorithm. In this paper, implementation of KECCAK algorithm. And SHA-2 On The ARM-11 processor, and compare performance.

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A Study on the Prospects of Using Schnorr Digital Signature in Blockchain

Na¹,

Kim²

2022

dcs

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An Implementation of an SHA-3 Hash Function Validation Program and Hash Algorithm on 16bit-UICC

Cited by 3 publications

References 0 publications

Chaining Optimization Methodology: A New SHA-3 Implementation on Low-End Microcontrollers

Chaining Optimization Methodology: A New SHA-3 Implementation on Low-End Microcontrollers

Implementation of SHA-3 Algorithm Based On ARM-11 Processors

A Study on the Prospects of Using Schnorr Digital Signature in Blockchain

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