An IEEE 802.15.4g SUN FSK RF CMOS transceiver for Smart Grid and CEs

Lee, Seung Sik; Choi, Sang Sung; Kim, Jae Young; Lee, Kang-Yoon

doi:10.1109/icce-berlin.2013.6698039

Cited by 2 publications

(8 citation statements)

References 5 publications

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“…Moreover PLL phase margin should be considered for the stable PLL operation. Typically bandwidth is controlled externally or set to be extremely large to cover the range [6,7]. These schemes have critical issues, for instance, external components should be attached or unwanted current consumption is additionally used.…”

Section: The Coarse Tuning Loop and Automatic Phase Margin Compensatimentioning

confidence: 99%

“…AAC_OUT is used to adjust the Negative-gm value of VCO. As a result, the phase noise performance of the VCO can be improved by adjusting the output swing to the target value with respect to the PVT variation [6].…”

Section: Phase-locked Loopmentioning

confidence: 99%

“…On the contrary, when the output of VCO has a smaller input, the AAC_OUT voltage is decreased in order to increase negative-gm. The compensation capacitor C C is used for the stable operation of negative-feedback [6].…”

Section: Phase-locked Loopmentioning

confidence: 99%

“…The AAC_OUT of the AAC loop is automatically controlled to maintain the amplitude at the pre-determined value [6].…”

Section: Phase-locked Loopmentioning

confidence: 99%

“…In order to obtain high power gain with a small DC current, a class-AB type DA is adopted. A cascode amplifier structure is adopted to guarantee the stability by isolating the input and output under the high output power condition [6].…”

Section: Modulation Filtermentioning

confidence: 99%

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A design of 50/150/200 kbps, low power FSK transceiver using phase-locked loop with programmable loop bandwidth and integrated SPDT for IEEE 802.15.4g application

Kim

Lee

et al. 2015

Analog Integr Circ Sig Process

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This paper presents a 50/150/200 kbps, low power transceiver with one-point modulation and integrated single pole double throw (SPDT) switch for IEEE 802.15.4g application. To ensure that the proposed low power transceiver can operate at a multi data rate, multi data-rate (50/150/200 kbps) frequency shift keying (FSK) modulation is implemented using a phase-locked loop (PLL) with a programmable loop bandwidth. The bandwidth switching scheme is combined with the programmable loop bandwidth to support the high data rate in the PLL of the transmitter. In the receiver, the SPDT switch is integrated to share the antenna and matching network between the transmitter and receiver, thus minimizing the system cost. Also the active-RC band pass filter with the programmable bandwidth is designed to support the data rates of 50, 150, and 200 kbps. The capacitors in each data rate are shared efficiently to minimize the die area. The FSK transmitter is implemented using 0.18 lm 1-poly 6-metal complementary metal-oxide semiconductor technology. The die area of the transceiver is 4.0 mm 2 . The power consumption of the transmitter and receiver are 54 and 25 mW, respectively, when the output power level of the transmitter is ?10.17 dBm at 1.8 V supply voltage. The phase noise of the PLL output at 1.8462 GHz is -118.13 dBc/Hz with a 1 MHz offset.

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Section: The Coarse Tuning Loop and Automatic Phase Margin Compensatimentioning

confidence: 99%

Section: Phase-locked Loopmentioning

confidence: 99%

Section: Phase-locked Loopmentioning

confidence: 99%

“…The AAC_OUT of the AAC loop is automatically controlled to maintain the amplitude at the pre-determined value [6].…”

Section: Phase-locked Loopmentioning

confidence: 99%

Section: Modulation Filtermentioning

confidence: 99%

See 3 more Smart Citations

A design of 50/150/200 kbps, low power FSK transceiver using phase-locked loop with programmable loop bandwidth and integrated SPDT for IEEE 802.15.4g application

Kim

Lee

et al. 2015

Analog Integr Circ Sig Process

Self Cite

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A fully integrated ieee IEEE 802.15.4g MR-FSK SoC soc for smart utility network applications

Lee

Jeon

et al. 2014

IEEE Trans. Consumer Electron.

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This paper presents a fully integrated multi-rate and multi-regional frequency shift keying (MR-FSK) systemon-chip (SoC) in 180-nm CMOS technology compliant with IEEE 802.15.4g standard for smart utility network (SUN). This SoC integrates all blocks including 800/900 MHz RF/Analog transceiver, digital modem, medium access controller (MAC) and security functions. The total SoC die area is 4.8 mm x 3.5 mm. The transceiver power consumption is 57 mW in receiving mode and 41 mW -79 mW in transmitting mode, while the digital part consumes 19.5 mW. The implemented SoC exceeds the sensitivity requirements of IEEE 802.15.4g standard and is suitable for long-range and low-duty cycled SUN applications, such as advanced metering infrastructure (AMI) 1 .

show abstract

An IEEE 802.15.4g SUN FSK RF CMOS transceiver for Smart Grid and CEs

Cited by 2 publications

References 5 publications

A design of 50/150/200 kbps, low power FSK transceiver using phase-locked loop with programmable loop bandwidth and integrated SPDT for IEEE 802.15.4g application

A design of 50/150/200 kbps, low power FSK transceiver using phase-locked loop with programmable loop bandwidth and integrated SPDT for IEEE 802.15.4g application

A fully integrated ieee IEEE 802.15.4g MR-FSK SoC soc for smart utility network applications

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