An Hybrid Architecture for consolidating mixed criticality applications on multicore systems

Avramenko, Serhiy; Esposito, Stefano; Violante, M.; Sozzi, M.; Traversone, Massimo; Binello, Marco; Terrone, Marco

doi:10.1109/iolts.2015.7229823

“…That architecture was adapted to the mixed criticality avionic use case and tested by Avramenko et al [11]. The implementation was based on a type-1 hypervisor granting isolation of applications in resource partitions.…”

Section: Previous Workmentioning

confidence: 99%

“…The architecture proposed in this paper, is built on top of the one proposed by Esposito and Violante [10] and uses results of Avramenko et al [11] with some additions and modifications. This paper is an extension of Esposito et al [12].…”

Section: Previous Workmentioning

confidence: 99%

On the Consolidation of Mixed Criticalities Applications on Multicore Architectures

Esposito

¹

,

Violante

²

2017

Self Cite

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In this paper we propose a hybrid solution to ensure results correctness when deploying several applications with different safety requirements on a single multi-core-based system. The proposed solution is based on lightweight hardware redundancy, implemented using smart watchdogs and voter logic, combined with software redundancy. Two techniques of software redundancy are used: the first one is software temporal triple modular redundancy, used for those tasks with low criticality and no real-time requirement. The second software redundancy technique is triple module redundancy for tasks with high criticality and real-time requirements, assisted by a hardware voter. A hypervisor is used to separate each task in the system in an independent resource partition, thus ensuring that no functional interference is occurring. The proposed solution has been evaluated through hardware and software fault injection on two hardware platforms, featuring a dual-core processor and a quad-core processor respectively. Results show a high fault tolerance achieved using the proposed architecture.

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“…The resources are memory areas which can represent either memory-mapped hardware peripherals, or actual instruction and data memory. In Avramenko et al [2015], a type-1 hypervisor has been used to implement a resource partitioning on a dual-core microprocessor. The system was designed to implement isolation of two applications running at different levels of assurance, and fault tolerance for both hardware and software faults.…”

Section: Related Workmentioning

confidence: 99%

A Novel Method for Online Detection of Faults Affecting Execution-Time in Multicore-Based Systems

Esposito

¹

,

Violante

²

,

Sozzi

³

et al. 2017

ACM Trans. Embed. Comput. Syst.

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11

0

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This paper proposes a bounded interference method, based on statistical evaluations, for online detection and tolerance of any fault capable of causing a deadline miss. The proposed method requires data that can be gathered during the profiling and worst-case execution time (WCET) analysis phase. This paper describes the method, its application, and then it presents an avionic mixed-criticality use case for experimental evaluation, considering both dual-core and quad-core platforms. Results show that faults that can cause a timing violation are correctly identified; other faults that do not introduce a significant temporal interference can be tolerated to avoid high recovery overheads. • Computer Systems Organization Dependable and fault-tolerant systems and networks • Applied computing Physical sciences and engineering Aerospace.

show abstract

“…The architecture proposed in this paper, is built on top of the one proposed by Esposito and Violante [10] and uses results of Avramenko et al [11] with some additions and modifications. This paper is an extension of Esposito et al [12].…”

Section: Previous Workmentioning

confidence: 99%

On the consolidation of mixed criticalities applications on multicore architectures

Esposito

¹

,

Avramenko

²

,

Violante

³

2016

2016 17th Latin-American Test Symposium (LATS)

Self Cite

2

0

View full text Add to dashboard Cite

In this paper we propose a hybrid solution to ensure results correctness when deploying several applications with different safety requirements on a single multi-core-based system. The proposed solution is based on lightweight hardware redundancy, implemented using smart watchdogs and voter logic, combined with software redundancy. Two techniques of software redundancy are used: the first one is software temporal triple modular redundancy, used for those tasks with low criticality and no real-time requirement. The second software redundancy technique is triple module redundancy for tasks with high criticality and real-time requirements, assisted by a hardware voter. A hypervisor is used to separate each task in the system in an independent resource partition, thus ensuring that no functional interference is occurring. The proposed solution has been evaluated through hardware and software fault injection on two hardware platforms, featuring a dual-core processor and a quad-core processor respectively. Results show a high fault tolerance achieved using the proposed architecture.

show abstract

An Hybrid Architecture for consolidating mixed criticality applications on multicore systems

Cited by 14 publications

References 3 publications

On the Consolidation of Mixed Criticalities Applications on Multicore Architectures

On the Consolidation of Mixed Criticalities Applications on Multicore Architectures

A Novel Method for Online Detection of Faults Affecting Execution-Time in Multicore-Based Systems

On the consolidation of mixed criticalities applications on multicore architectures

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