An HBT Four-Cell Monolithic Stacked Power Amplifier

Design and Analysis of Stacked Power Amplifier in Series-Input and Series-Output Configuration

“…In this case, the cells farther down the transformer ladder contribute less to the overall output, and the efficiency drops as the number of cells increases. From (12) and assuming that the loss at each transformer is equal, the power combination efficiency of the stack of an -cell stack is (15) In (15), represents the voltage loss of each transformer. Applying (15) to the incremental efficiency drop constraint of (14) will give the upper limit of the number of cells at various voltage loss (16) Using (15), the power combination efficiency versus the number of cells with different transformer efficiencies are plotted in Fig.…”

“…From (12) and assuming that the loss at each transformer is equal, the power combination efficiency of the stack of an -cell stack is (15) In (15), represents the voltage loss of each transformer. Applying (15) to the incremental efficiency drop constraint of (14) will give the upper limit of the number of cells at various voltage loss (16) Using (15), the power combination efficiency versus the number of cells with different transformer efficiencies are plotted in Fig. 5, and (16) dictates the upper cell limit at various transformer efficiencies.…”

“…For eight cells, the requirement for efficient combining efficiency is more stringent, a 20 phase delay will result in only 50% efficiency, which is only as good as four ideal devices, and in essence, poorer than a seven-cell stack from the constraint of (18). A graphic representation of this concept was presented in [15].…”

“…A modification of the transformer-coupled stack has recently been implemented in a 2m HBT [15], shown in Fig. 1(c).…”