An FPGA-Oriented Baseband Modulator Architecture for 4G/5G Communication Scenarios

Abstract

The next evolution in cellular communications will not only improve upon the performance of previous generations, but also represent an unparalleled expansion in the number of services and use cases. One of the foundations for this evolution is the design of highly flexible, versatile, and resource-/power-efficient hardware components. This paper proposes and evaluates an FPGA-oriented baseband processing architecture suitable for communication scenarios such as non-contiguous carrier aggregation, centralized Cloud Radio Access Network (C-RAN) processing, and 4G/5G waveform coexistence. Our system is upgradeable, resource-efficient, cost-effective, and provides support for three 5G waveform candidates. Exploring Dynamic Partial Reconfiguration (DPR), the proposed architecture expands the design space exploration beyond the available hardware resources on the Zynq xc7z020 through hardware virtualization. Additionally, Dynamic Frequency Scaling (DFS) allows for run-time adjustment of processing throughput and reduces power consumption up to 88%. The resource overhead for DPR and DFS is residual, and the reconfiguration latency is two orders of magnitude below the control plane latency requirements proposed for 5G communications.waveforms (FBMC, UFMC, GFDM) intermingled with a variety of 3G and 4G waveforms" [3]. In heavily used portions of the spectrum, such as the sub-6 GHz band, multi-waveform coexistence requires Dynamic Spectrum Access (DSA) and Carrier Aggregation (CA) techniques to achieve a more efficient spectrum utilization [1].Other important factors in 5G NR are cost minimization and energy efficiency. Cloud Radio Access Networks (C-RANs) attempt to achieve a more efficient energy consumption and resource allocation by deploying a central Baseband processing Unit (BBU) that serves multiple Remote Radio Heads (RRHs) [4]. This network architecture relies on reconfigurable hardware modules to implement BBUs supporting the different access technologies and modes of operation used by RRHs.The realization of the 5G vision will strongly rely on the design of hardware infrastructure adjusted to the challenges imposed by future wireless communications. Regarding digital baseband processing, hardware designs should be: (1)flexible to support multiple services requirements, waveforms, and numerologies; (2) evolvable/forward-compatible to be easily upgradeable with new functionalities and future modes of operation, thus extending the system's duty lifetime; (3) energy-efficient and (4) cost-effective. FPGAs are convenient platforms to design systems with these characteristics. Apart from their capacity for parallel intensive computation, FPGAs feature a high degree of flexibility not only at design time, but also at runtime, through Dynamic Partial Reconfiguration (DPR) [5]: the ability to reconfigure portions of FPGA logic fabric (reconfigurable regions) while the other portions remain unchanged and running. This increases the FPGA functional density, as mutually-exclusive circuits/functionalities are implemented o...

Flexible Baseband Modulator Architecture for Multi-Waveform 5G Communications

“…Therefore, instead of the high-performance pipelined IFFT architectures adopted for the OFDM and FBMC datapaths, low-resource memory-based FFT architectures are adopted in the UFMC modulator. The memory-based architecture adopted here is detailed in [30]. The upsampler architecture and operation is similar to the one used for frequency spreading in FBMC modulation.…”

The Improved Division-Less MT-Type Velocity Estimation Algorithm for Low-Cost FPGAs

“…The MT-type division-less algorithm, as shown in Equations (14) and (15), can be described graphically by the block scheme in Figure 4. Obviously, the inputs in the algorithm are the sampled encoder position x kand the elapsed time intervalsince the recent encoder pulse, i.e., δt k , whereas the main output of the algorithm is the estimated velocityv k .…”

“…x x x , and ˆk v is the value of estimated average velocity in the k-th sampling period. The MT-type division-less algorithm, as shown in Equations (14) and (15), can be described graphically by the block scheme in Figure 4. Obviously, the inputs in the algorithm are the sampled encoder position k…”

“…They offer possibilities for integrating complex hardware systems and their interfaces into a single FPGA chip. FPGA devices have reached a high maturity level in terms of performance, power consumption, and cost, which makes them suitable for different application fields [2] that involve sensor systems [3,4], control systems [5,6], haptic interfaces [7,8], robotics [9][10][11], and other advanced electronic devices for signal processing and communications, e.g., [12][13][14][15]. They can also be useful for advanced velocity estimation methods, since they can easily be designed for custom signal conditioning and provide fast dedicated digital logic [16].…”

Layered Inter-Cluster Cooperation Scheme for Backhaul-Constrained C-RAN Uplink Systems in the Presence of Inter-Cluster Interference

“…Cloud radio access network (C-RAN) systems have a potential of reducing the capital and operating expenditures and of improving spectral and energy efficiency. These benefits can be realized by centralized baseband signal processing at baseband processing unit (BBU) pools [ 1 , 2 , 3 ]. However, it is challenging to reliably transfer baseband samples on fronthaul links that connect distributed radio units (RUs) to nearby BBUs particularly for broadband communication systems.…”