An FPGA Implementation of High-Speed Flexible 27-Mbps 8-StateTurbo Decoder

Abstract

In this paper, we propose a flexible turbo decoding algorithm for a high order modulation scheme that uses a standard half‐rate turbo decoder designed for binary quadrature phase‐shift keying (B/QPSK) modulation. A transformation applied to the incoming I‐channel and Q‐channel symbols allows the use of an off‐the‐shelf B/QPSK turbo decoder without any modifications. Iterative codes such as turbo codes process the received symbols recursively to improve performance. As the number of iterations increases, the execution time and power consumption also increase. The proposed algorithm reduces the latency and power consumption by combination of the radix‐4, dual‐path processing, parallel decoding, and early‐stop algorithms. We implement the proposed scheme on a field‐programmable gate array and compare its decoding speed with that of a conventional decoder. The results show that the proposed flexible decoding algorithm is 6.4 times faster than the conventional scheme.

A Programmable Max‐Log‐MAP Turbo Decoder Implementation

“…Naturally, the more parallelism is used the higher throughput can be obtained. For example, by applying radix-4 algorithms the decoders in [10,12] can process more than one trellis stage in one clock cycle. A slightly more flexible solution is to use monolithic accelerator, which is accompanied with a fully programmable processor like in [13,14].…”

“…Unfortunately, [10][11][12][13] do not provide details of the applied parallel access method. In [15,16] a conflict free access scheme for extrinsic information memory is developed, but the studies do not present turbo decoder implementation applying the memory access scheme.…”

“…The implementations [10,12] in Table 3 have C stage < 1, as they apply the radix-4 algorithm. The architecture in [12] includes two component decoders. The decoders in [36,37] support also Viterbi decoding.…”

A novel state metric normalization technique for high-throughput maximum-a-posteriori-probability decoder

“…The proposed MAP decoder is implemented on FPGA and the details are discussed. There are hardware implementations of high speed MAP decoder existing in the literature [5], [6], [7], [8], [9], [10]. Finally, throughput and maximum clock frequency of these existing implementations are compared with the proposed MAP decoder implementation.…”