An FPGA Connect6 Solver with a two-stage pipelined evaluation

Watanabe, Takahiro; Moriwaki, Retsu; Yamaji, Youhei; Kamikubo, Yuki; Torigai, Yuki; Nihira, Yuki; Yoza, Takashi; Ueno, Yuichiro; Aoyama, Yuji; Watanabe, Minoru

doi:10.1109/fpt.2011.6133249

Cited by 6 publications

(5 citation statements)

References 7 publications

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“…"Threat" is defined as the number of the connections of five or four stones which can become checkmate only with one more move. Several FPGA-based Connect6 solvers were reported at the design competition of ICFPT'11 [9,11,12,15]. Vipin et al presented threat-based implementation, which is based on cell-weight computation and threat detection [11].…”

Section: Related Workmentioning

confidence: 98%

“…Their design computes scores in parallel with small modules for 6x6 sub-boards, however, tree-search is not introduced. Watanabe et al proposed a FPGAbased solver based on the mini-Max search with the alpha-beta pruning [12]. For move evaluation, they introduced the two-stage pipelined-evaluation method using a zero-evaluation function and a detail-evaluation function.…”

Section: Related Workmentioning

confidence: 99%

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FPGA-based Connect6 solver with hardware-accelerated move refinement

Sano

Yoshiaki

2012

SIGARCH Comput. Archit. News

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Connect6 is a two-player game similar to Go-Moku, which was introduced in 2003. Since placing two stones in each turn makes a huge game-tree, we require some acceleration techniques for a solver based on a typical approach to search the tree. This paper presents an FPGA-based Connect6 solver with two-level move refinement. The solver has the dedicated hardware to accelerate the move refinement by exploiting various parallelism with a systolic array, linear arrays, and multiple score-calculation units. Implementation with a low-end FPGA demonstrates that the accelerator allows the two-level move refinement in the FPGA-based solver running at 90 MHz to be 103695 and 414 times faster than equivalent software implementation with NIOS II soft processor on the FPGA and Intel Core i7 processor operating at 2.93 GHz, respectively.

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Section: Related Workmentioning

confidence: 98%

Section: Related Workmentioning

confidence: 99%

FPGA-based Connect6 solver with hardware-accelerated move refinement

Sano

Yoshiaki

2012

SIGARCH Comput. Archit. News

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“…Other games like Connect6, Blokus and Go have also been implemented by the FPGA developer's community. The works presented in [15][16][17] detail FPGA-based implementations and comparisons with software, reporting speedups of one or even two orders of magnitude. In the light of these results, it is clear that FPGAs outperform general purpose processors in these games.…”

Section: Related Workmentioning

confidence: 99%

Accelerating Board Games Through Hardware/Software Codesign

Olivito

Resano

Briz

2017

IEEE Trans. Comput. Intell. AI Games

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Board games applications usually offer a great user experience when running on desktop computers. Powerful high performance processors working without energy restrictions successfully deal with the exploration of large game trees, delivering strong play to satisfy demanding users. However, nowadays, more and more game players are running these games on smartphones and tablets, where the lower computational power and limited power budget yield a much weaker play. Recent Systems-on-a-Chip include programmable logic tightly coupled with general-purpose processors enabling the inclusion of custom accelerators for any application to improve both performance and energy efficiency. In this article, we analyze the benefits of partitioning the artificial intelligence of board games into software and hardware. We have chosen as case studies three popular and complex board games, Reversi, Blokus, and Connect-6. The designs analyzed include hardware accelerators for board processing which improve performance and energy efficiency by an order of magnitude leading to much stronger and battery-aware applications. The results demonstrate that the use of hardware/software co-design to develop board games allows sustaining or even improving the user experience across platforms while keeping power and energy low.

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“…The code uses the dual-port block memory (BRAM) units for display and game code controls. For the Connect6 Solver, the VHDL code is implemented on a DE2-115 Development and Education board having the Cyclone IV processor [12]. The code again uses the BRAM units (50.7%) and consumes the 92.6% of the logic elements.…”

Section: Introductionmentioning

confidence: 99%

“…Thanks to the availability of one-to-one mapping and the spatial and temporal parallelism of the FPGAs, they are often used to implement real-time image processing applications [6][7][8][9][10]. One such application is the game code implementation on FPGAs such as Tetris [11], Connect6 [12][13], Blokus duo [14][15][16], Trax [17] and Pong [18][19]. In [11], Kuo et al design a tetris game code using the Spartan 3AN FPGA starter board of Xilinx.…”

Section: Introductionmentioning

confidence: 99%

VHDL İle Tam Gömülü Bi̇r Tetri̇s Oyunu Gerçekleşti̇rmesi̇

Polat¹

2020

Ömer Halisdemir Üniversitesi Mühendislik Bilimleri Dergisi

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In this paper, a Tetris game code which runs on an FPGA development and education board is synthesized. To this end, an original Tetris game code that works solely on the FPGA board is designed in VHDL hardware description language. The novelty of this design lies in the fact that the Tetris code does not use any SRAM modules for storage unlike other embedded Tetris implementations published to date. What is more, the code uses a tile-mapped scheme in which the code groups certain pixels as a tile. Thus, a 1-bit register is enough for the current value of all the pixels that fall in the tile which improves the speed of the code and simplifies the design procedure. The code is written using VHDL hardware description language. Though Altera DE0 development and education board is used for the implementation, thanks to the usage of only the standard VHDL functions, the code can run on any other FPGA boards.

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An FPGA Connect6 Solver with a two-stage pipelined evaluation

Cited by 6 publications

References 7 publications

FPGA-based Connect6 solver with hardware-accelerated move refinement

FPGA-based Connect6 solver with hardware-accelerated move refinement

Accelerating Board Games Through Hardware/Software Codesign

VHDL İle Tam Gömülü Bi̇r Tetri̇s Oyunu Gerçekleşti̇rmesi̇

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