An FPGA-Based Tightly Coupled Accelerator for Data-Intensive Applications

Yoshimi, Masato; Kudo, Ryu; Oge, Yasin; Terada, Yuta; Irie, Hidetsugu; Yoshinaga, Tsutomu

doi:10.1109/mcsoc.2014.47

Cited by 8 publications

(4 citation statements)

References 17 publications

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“…Reconfigurable many core architectures for data analytics have been proposed, including the use of FPGAs for data-intensive applications via the strong coupling between storage and FPGA [14] and switching of hardware and software threads for a heterogeneous system involving a CPU and reconfigurable computing units [15]. It focused on the run-time management of tasks but did not provide insight on the architectural challenges of processing elements.…”

Section: Background Workmentioning

confidence: 99%

NanoStreams: A Microserver Architecture for Real-Time Analytics on Fast Data Streams

Minhas

Russell

Kaloutsakis

et al. 2018

IEEE Trans. Multi-Scale Comp. Syst.

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Abstract-Ever increasing power consumption has created great interest in energy-efficient microserver architectures but they lack the computational, networking and storage power necessary to cope with real-time data analytics. We propose NanoStreams, an integrated architecture comprising an ARM-based microserver, coupled via a novel, low latency network interface, Nanowire, to a Analytics-on-Chip architecture implemented on Field Programmable Gate Array (FPGA) technology; the architecture comprises ARM cores for performing low latency transactional processing, integrated with programmable, energy efficient Nanocore processors for high-throughput streaming analytics. The paper outlines the complete system architecture, hardware level detail, compiler, network protocol, and programming environment. We present experiments with an industrial workload from the financial services sector, comparing a state-of-the-art server based on Intel Sandy Bridge processors, an ARM based Calxeda ECS-1000 microserver and ODROID XU3 node, with the NanoStreams microserver architecture. For end-to-end workload, the NanoStreams microserver achieves energy savings up to 10.7×, 5.87× and 5× compared to the Intel server, Calxeda microserver and ODROID node respectively.

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Section: Background Workmentioning

confidence: 99%

NanoStreams: A Microserver Architecture for Real-Time Analytics on Fast Data Streams

Minhas

Russell

Kaloutsakis

et al. 2018

IEEE Trans. Multi-Scale Comp. Syst.

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“…This system is composed of a single conventional microprocessor and a huge reconfigurable logic [26]. Yoshimi et al [27] proposes an FPGA based accelerator that is tightly coupled with the flash storage and optical network interface. It is a complete system which has high level resource sharing in terms of accesses from FPGA.…”

Section: B Custom and Reconfigurable Logic Acceleratorsmentioning

confidence: 99%

Hardware accelerator design for data centers

Yesil¹,

Özdal²,

Ayupov³

et al. 2015

2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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As the size of available data is increasing, it is becoming inefficient to scale the computational power of traditional systems. To overcome this problem, customized applicationspecific accelerators are becoming integral parts of modern system on chip (SOC) architectures. In this paper, we summarize existing hardware accelerators for data centers and discuss the techniques to implement and embed them along with the existing SOCs.

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“…It is well known that application-specific hardware can perform tasks more efficiently than software running on a general purpose CPU. Accelerators for many applications such as image recognition [45], computer vision [22], key-value stores [14,30], data warehouses [26], big data [10,18,44], deep learning [12], neural networks [23] (and many more) are commonly used to reduce overall system cost and increase performance orders of magnitude beyond the capabilities of a general-purpose instruction set.…”

Section: Introductionmentioning

confidence: 99%

“…In the past, only the most computationally-intensive portions of the program were offloaded to accelerators. More recently, it is becoming common to offload entire applications to accelerators such as SSDs, GPUs and FPGAs that the CPU is needed only for initial setup and error handling [8,10,11,14,16,30,44]. We believe that systems have evolved to the point that the CPU is an appendage that can be completely removed.…”

Section: Introductionmentioning

confidence: 99%

The last CPU

Nider

Fedorova

2021

Proceedings of the Workshop on Hot Topics in Operating Systems

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Since the end of Dennard scaling and Moore's Law have been foreseen, specialized hardware has become the focus for continued scaling of application performance. Programmable accelerators such as smart memory, smart disks, and smart NICs are now being integrated into our systems. Many accelerators can be programmed to process their data autonomously and require little or no intervention during normal operation. In this way, entire applications are offloaded, leaving the CPU with the minimal responsibilities of initialization, coordination and error handling.We claim that these responsibilities can also be handled in simple hardware other than the CPU and that it is wasteful to use a CPU for these purposes. We explore the role and the structure of the OS in a system that has no CPU and demonstrate that all necessary functionality can be moved to other hardware. We show that almost all of the pieces for such a system design are already available today. The responsibilities of the operating system must be split between self-managing devices and a system bus that handles privileged operations. CCS CONCEPTS• Computer systems organization → Peer-to-peer architectures.

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An FPGA-Based Tightly Coupled Accelerator for Data-Intensive Applications

Cited by 8 publications

References 17 publications

NanoStreams: A Microserver Architecture for Real-Time Analytics on Fast Data Streams

NanoStreams: A Microserver Architecture for Real-Time Analytics on Fast Data Streams

Hardware accelerator design for data centers

The last CPU

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