An FPGA-based SOM circuit architecture for online learning of 64-QAM data streams

Sousa, Miguel de Abreu de Angelo; Pires, Ricardo; Perseghini, Sara D. dos S.; Del-Moral-Hernandez, Emílio

doi:10.1109/ijcnn.2018.8489518

Cited by 4 publications

(3 citation statements)

References 25 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Quadrature amplitude modulation (QAM) has been applied in many communication systems. Abreu de Sousa et al [24] proposed an FPGA-based hardware SOM to detect 64-QAM symbols. The use of a SOM in Quadrature/In-phase pair detection enabled the QAM constellation to be adjusted continuously with no supervision.…”

Section: Related Workmentioning

confidence: 99%

Place-and-Route Analysis of FPGA Implementation of Nested Hardware Self-Organizing Map Architecture

Hikawa

2023

Electronics

View full text Add to dashboard Cite

Self-organizing map (SOM) is a type of artificial neural network that provides a nonlinear mapping from a given high-dimensional input space to a low-dimensional map of neurons for clustering. The clustering of high-dimensional vectors is too slow for SOM when implemented in software. In such cases, an application-specific hardware SOM accelerator is highly desirable. Field-programmable gate array (FPGA) implementation is a popular platform to implement hardware SOM. In our previous work, a nested hardware SOM architecture, which has a homogeneous modular structure to enhance expandability, was proposed. This paper investigates the impact of the nested hardware SOM on FPGA implementation tools that perform logic synthesis, place, and route (PAR). Experiments revealed that the nested architecture provided better results in resource usage and performance. FPGA resource usage of the nested architecture was 97.2% of that of the flat design on average. Importantly, the nested architecture operated at 10% higher clock frequencies compared to flat SOM designs. In addition, the pipeline computation was improved by increasing the pipeline stages so that it operates with a higher clock frequency. The operable clock frequency was 81 MHz, which was 21 MHz higher than its predecessor.

show abstract

Section: Related Workmentioning

confidence: 99%

Place-and-Route Analysis of FPGA Implementation of Nested Hardware Self-Organizing Map Architecture

Hikawa

2023

Electronics

View full text Add to dashboard Cite

show abstract

“…Hardware SOMs handling low-dimensional vectors, such as [11], [24], [26], use registers for storing the weight vector elements. Fig.…”

Section: E Weight Vector Updatementioning

confidence: 99%

A Survey of Hardware Self-Organizing Maps

Jovanovic

Hikawa

2023

IEEE Trans. Neural Netw. Learning Syst.

View full text Add to dashboard Cite

Self-organizing feature maps (SOMs) are commonly used technique for clustering and data dimensionality reduction in many application fields. Indeed, their inherent property of topology preservation and unsupervised learning of processed data without any prior knowledge put them in the front of candidates for data reduction in the Internet of Things (IoT) and big data (BD) technologies. However, the high computational cost of SOMs limits their use to offline approaches and makes the online real-time high-performance SOM processing more challenging and mostly reserved to specific hardware implementations. In this article, we present a survey of hardware (HW) SOM implementations found in the literature so far: the most widely used computing blocks, architectures, design choices, adaptation, and optimization techniques that have been reported in the field of hardware SOMs. Moreover, we give an overview of main challenges and trends for their ubiquitous adoption as hardware accelerators in many application fields. This article is expected to be useful for researchers in the areas of artificial intelligence, hardware architecture, and system design.

show abstract

“…Kim et al [21] investigated an energy-efficient hardware architecture of SOM for electrocardiogram (ECG), and they presented its implementation in 65nm CMOS. Quadrature Amplitude Modulation (QAM) has been applied in many communication systems, and Sousa et al [22] proposed a new FPGA-based SOM to detect 64-QAM symbols. The use of SOM in the Quadrature/Inphase pair detection allowed the continuous adjustment to the QAM constellation with no supervision, and bandwidth could be saved and training data retransmission was no longer necessary.…”

mentioning

confidence: 99%

Hardware Self-Organizing Map Based on Digital Frequency-Locked Loop and Triangular Neighborhood Function

Hikawa

2021

IEEE Trans. Circuits Syst. I

View full text Add to dashboard Cite

This paper proposes a unique hardware architecture for a self-organizing map (SOM) that mimics the biological brain by using pulse mode operation. In the proposed SOM, vector elements are given as in the form of frequency modulated signals, and digital frequency-locked loops (DFLLs) in neurons handle the computations of the vector elements. The SOM is trained by unsupervised learning, where the winner neuron that has the nearest weight vector is found first. In the proposed SOM, the winner neuron is found by counting cycle slips between the signals that carry input and weight vectors. After the winner neuron is found, weight vectors selected by a neighborhood function are updated toward the input vector. Triangular neighborhood function that is implemented by using an attenuating enable signal for the DFLLs, is employed. To evaluate the proposed SOM and its building components, VHDL simulations and experiments using an FPGA were conducted. Compared to the previous work, the operation speed and learning capability were significantly improved. Novelty of the proposed architecture is it uniquely uses a pulse-based operation that mimics the biological brain, and it was verified that unsupervised learning can be realized with neurons communicating with each other using frequency modulated pulse signals.

show abstract

An FPGA-based SOM circuit architecture for online learning of 64-QAM data streams

Cited by 4 publications

References 25 publications

Place-and-Route Analysis of FPGA Implementation of Nested Hardware Self-Organizing Map Architecture

Place-and-Route Analysis of FPGA Implementation of Nested Hardware Self-Organizing Map Architecture

A Survey of Hardware Self-Organizing Maps

Hardware Self-Organizing Map Based on Digital Frequency-Locked Loop and Triangular Neighborhood Function

Contact Info

Product

Resources

About