Hardware Self-Organizing Map Based on Digital Frequency-Locked Loop and Triangular Neighborhood Function

Hikawa, Hiroomi

doi:10.1109/tcsi.2020.3046795

Cited by 4 publications

(3 citation statements)

References 52 publications

(83 reference statements)

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“…The last quarter ("Other" in Fig. 4) is the different attempt to use uncommon distance metrics for the HW SOM algorithm: modified Hamming distance [52], frequency comparison [25], dot product cosine [53], inner product [27], count of cycle slips [54], and so on.…”

Section: B Vector Distance Computationmentioning

confidence: 99%

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A Survey of Hardware Self-Organizing Maps

Jovanovic

Hikawa

2023

IEEE Trans. Neural Netw. Learning Syst.

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Self-organizing feature maps (SOMs) are commonly used technique for clustering and data dimensionality reduction in many application fields. Indeed, their inherent property of topology preservation and unsupervised learning of processed data without any prior knowledge put them in the front of candidates for data reduction in the Internet of Things (IoT) and big data (BD) technologies. However, the high computational cost of SOMs limits their use to offline approaches and makes the online real-time high-performance SOM processing more challenging and mostly reserved to specific hardware implementations. In this article, we present a survey of hardware (HW) SOM implementations found in the literature so far: the most widely used computing blocks, architectures, design choices, adaptation, and optimization techniques that have been reported in the field of hardware SOMs. Moreover, we give an overview of main challenges and trends for their ubiquitous adoption as hardware accelerators in many application fields. This article is expected to be useful for researchers in the areas of artificial intelligence, hardware architecture, and system design.

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Section: B Vector Distance Computationmentioning

confidence: 99%

“…For the winner search, a cycle slip detector is also employed. In [54], this DFLL-based SOM is improved by employing the triangular neighborhood function. This function is implemented by using pulsewidth-modulated signals spread from the winner neuron without multipliers.…”

Section: F Vector Representationmentioning

confidence: 99%

A Survey of Hardware Self-Organizing Maps

Jovanovic

Hikawa

2023

IEEE Trans. Neural Netw. Learning Syst.

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“…Compared to other existing AES transmission designs, the one described in this paper has a higher data throughput and takes up less space in the FPGA [23]. Rather than processing 16 bytes at a time, the proposed design processes 4 bytes at a time, resulting in a smaller footprint on the hardware [24].…”

Section: Introductionmentioning

confidence: 99%

Implementation of VLSI on Signal Processing-Based Digital Architecture Using AES Algorithm

Marimuthu¹,

Rajendran²,

Radhakrishnan³

et al. 2023

Computers, Materials &Amp; Continua

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Continuous improvements in very-large-scale integration (VLSI) technology and design software have significantly broadened the scope of digital signal processing (DSP) applications. The use of application-specific integrated circuits (ASICs) and programmable digital signal processors for many DSP applications have changed, even though new system implementations based on reconfigurable computing are becoming more complex. Adaptable platforms that combine hardware and software programmability efficiency are rapidly maturing with discrete wavelet transformation (DWT) and sophisticated computerized design techniques, which are much needed in today's modern world. New research and commercial efforts to sustain power optimization, cost savings, and improved runtime effectiveness have been initiated as initial reconfigurable technologies have emerged. Hence, in this paper, it is proposed that the DWT method can be implemented on a fieldprogrammable gate array in a digital architecture (FPGA-DA). We examined the effects of quantization on DWT performance in classification problems to demonstrate its reliability concerning fixed-point math implementations. The Advanced Encryption Standard (AES) algorithm for DWT learning used in this architecture is less responsive to resampling errors than the previously proposed solution in the literature using the artificial neural networks (ANN) method. By reducing hardware area by 57%, the proposed system has a higher throughput rate of 88.72%, reliability analysis of 95.5% compared to the other standard methods.

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