An FPGA-based platform for accelerated offline spike sorting

Gibson, Sarah; Judy, Jack W.; Marković, Dejan

doi:10.1016/j.jneumeth.2013.01.026

Cited by 27 publications

(30 citation statements)

References 11 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In the case of the spike sorting approach simulated here, the simplicity of the on-chip calculations indicates that the decrease in power consumption due to data reduction overcomes the power needs to perform those calculations. Based on the power requirements reported in low-power neural interfaces(Lopez et al, 2012, Gibson et al, 2013, Karkare et al, 2013, Wattanapanitch and Sarpeshkar., 2011, Rush and Troyk., 2012), we can estimate the power consumption of this hypothetical chip and assess its feasibility. Assuming an analog front-end (AFE) performing amplification, filtering, and ADC at 7 kHz and 10-bit resolution we estimate a spending of approximately 10 μW per channel only for this step (Wattanapanitch and Sarpeshkar., 2011).…”

Section: Resultsmentioning

confidence: 99%

“…Previous attempts to study the effect of different hardware compromises analysed the impact of dimensionality reduction (i.e. number of coefficients) for spike sorting (Gibson et al, 2013, Gibson et al, 2010), and the number of errors in a wireless protocol versus packet length (Aghagolzadeh and Oweiss., 2011). In line, Zhang and collaborators studied how sampling rate and resolution affect the reconstruction error after wireless data transmission (Zhang et al, 2012), whereas Thorbergsson and colleagues studied the effect of these parameters on offline processing outside the body (Thorbergsson et al, 2012).…”

Section: Discussionmentioning

confidence: 99%

See 1 more Smart Citation

Minimum requirements for accurate and efficient real-time on-chip spike sorting

Navajas

Barsakcioglu

Eftekhar

et al. 2014

Journal of Neuroscience Methods

View full text Add to dashboard Cite

show abstract

Section: Resultsmentioning

confidence: 99%

Section: Discussionmentioning

confidence: 99%

Minimum requirements for accurate and efficient real-time on-chip spike sorting

Navajas

Barsakcioglu

Eftekhar

et al. 2014

Journal of Neuroscience Methods

View full text Add to dashboard Cite

show abstract

“…Integrating a spike sorting algorithm into an IC to reduce system size was first demonstrated by Karkare et al in which a Euclidian distance based sorting algorithm was used [35,36]. Later, Gibson et al developed an FPGA system in which the spike sorting algorithm used by Rutishauser was implemented, increasing the sorting speed 25 fold, with a worst-case latency of 11 ms [34,37]. Park et al [38] designed a real-time spike sorting system based on Rutishauser with the abilities of online training and classification, their work also optimized memory usage during the template training phase.…”

Section: Introductionmentioning

confidence: 99%

Low-latency single channel real-time neural spike sorting system based on template matching

et al. 2019

View full text Add to dashboard Cite

Recent technical advancements in neural engineering allow for precise recording and control of neural circuits simultaneously, opening up new opportunities for closed-loop neural control. In this work, a rapid spike sorting system was developed based on template matching to rapidly calculate instantaneous firing rates for each neuron in a multi-unit extracellular recording setting. Cluster templates were first generated by a desktop computer using a non-parameter spike sorting algorithm (Super-paramagnetic clustering) and then transferred to a field-programmable gate array digital circuit for rapid sorting through template matching. Two different matching techniques–Euclidean distance (ED) and correlational matching (CM)–were compared for the accuracy of sorting and the performance of calculating firing rates. The performance of the system was first verified using publicly available artificial data and was further confirmed with pre-recorded neural spikes from an anesthetized Mongolian gerbil. Real-time recording and sorting from an awake mouse were also conducted to confirm the system performance in a typical behavioral neuroscience experimental setting. Experimental results indicated that high sorting accuracies were achieved for both template-matching methods, but CM can better handle spikes with non-Gaussian spike distributions, making it more robust for in vivo recording. The technique was also compared to several other off-line spike sorting algorithms and the results indicated that the sorting accuracy is comparable but sorting time is significantly shorter than these other techniques. A low sorting latency of under 2 ms and a maximum spike sorting rate of 941 spikes/second have been achieved with our hybrid hardware/software system. The low sorting latency and fast sorting rate allow future system developments of neural circuit modulation through analyzing neural activities in real-time.

show abstract

“…A drawback of some FPGA circuits is that they may utilize high area resources and/or dissipate high power. The FPGA systems are then mainly adopted only for offline spike sorting systems [ 8 ]. An alternative to the FPGA for hardware implementation is based on the application-specific integrated circuit (ASIC) [ 9 ].…”

Section: Introductionmentioning

confidence: 99%

An Efficient Hardware Circuit for Spike Sorting Based on Competitive Learning Networks

Chen

Hwang

2017

Sensors

View full text Add to dashboard Cite

This study aims to present an effective VLSI circuit for multi-channel spike sorting. The circuit supports the spike detection, feature extraction and classification operations. The detection circuit is implemented in accordance with the nonlinear energy operator algorithm. Both the peak detection and area computation operations are adopted for the realization of the hardware architecture for feature extraction. The resulting feature vectors are classified by a circuit for competitive learning (CL) neural networks. The CL circuit supports both online training and classification. In the proposed architecture, all the channels share the same detection, feature extraction, learning and classification circuits for a low area cost hardware implementation. The clock-gating technique is also employed for reducing the power dissipation. To evaluate the performance of the architecture, an application-specific integrated circuit (ASIC) implementation is presented. Experimental results demonstrate that the proposed circuit exhibits the advantages of a low chip area, a low power dissipation and a high classification success rate for spike sorting.

show abstract

An FPGA-based platform for accelerated offline spike sorting

Cited by 27 publications

References 11 publications

Minimum requirements for accurate and efficient real-time on-chip spike sorting

Minimum requirements for accurate and efficient real-time on-chip spike sorting

Low-latency single channel real-time neural spike sorting system based on template matching

An Efficient Hardware Circuit for Spike Sorting Based on Competitive Learning Networks

Contact Info

Product

Resources

About