Low-latency single channel real-time neural spike sorting system based on template matching

Abstract

Recent technical advancements in neural engineering allow for precise recording and control of neural circuits simultaneously, opening up new opportunities for closed-loop neural control. In this work, a rapid spike sorting system was developed based on template matching to rapidly calculate instantaneous firing rates for each neuron in a multi-unit extracellular recording setting. Cluster templates were first generated by a desktop computer using a non-parameter spike sorting algorithm (Super-paramagnetic clustering) and then transferred to a field-programmable gate array digital circuit for rapid sorting through template matching. Two different matching techniques–Euclidean distance (ED) and correlational matching (CM)–were compared for the accuracy of sorting and the performance of calculating firing rates. The performance of the system was first verified using publicly available artificial data and was further confirmed with pre-recorded neural spikes from an anesthetized Mongolian gerbil. Real-time recording and sorting from an awake mouse were also conducted to confirm the system performance in a typical behavioral neuroscience experimental setting. Experimental results indicated that high sorting accuracies were achieved for both template-matching methods, but CM can better handle spikes with non-Gaussian spike distributions, making it more robust for in vivo recording. The technique was also compared to several other off-line spike sorting algorithms and the results indicated that the sorting accuracy is comparable but sorting time is significantly shorter than these other techniques. A low sorting latency of under 2 ms and a maximum spike sorting rate of 941 spikes/second have been achieved with our hybrid hardware/software system. The low sorting latency and fast sorting rate allow future system developments of neural circuit modulation through analyzing neural activities in real-time.

FPGA Design Integration of a 32-Microelectrodes Low-Latency Spike Detector in a Commercial System for Intracortical Recordings

“…[29] is the most similar, being developed on the same recording system, while works from Wang, P.K. et al [24] and Luan, S. et al [30] use only the same headstage. Particularly, the latter is a battery-powered standalone platform that logs data on a SD card and therefore, could be considered belonging to another category of devices.…”

“…The k NEO, on which the SNEO is based, gives an instantaneous estimation of the energy contained in a signal oscillation. Thanks to the energy dependent answer, the SNEO became widely used for the spike detection task and is still one of the preferred spike detector operators when going on real-time processing [22][23][24][25]. It fits very well to a real-time and low-latency application since it does not require any training phase and has a small footprint on the resource usage nevertheless the good performances, as proved and compared in [20].…”

A Low Power 1024-Channels Spike Detector Using Latch-Based RAM for Real-Time Brain Silicon Interfaces

“…In Wang et al [35], an FPGA closed loop application with both spike detector and spike sorting is presented. The detection is based on non-linear energy operator (NEO) with a unitary tuning parameter and without introducing smoothing process.…”

Parallel architecture to accelerate superparamagnetic clustering algorithm

“…Comparing to other data clustering algorithms, such as support vector machine or K‐means [5], SPC is a density‐based method in which SPC clusters are self‐organised according to the mutual interaction inversely proportional to the Euclidian distances between neighbouring data points in the feature space. In addition, SPC has a ‘temperature’ parameter, which is used to describe how strong the mutual interaction is – the higher the temperature, the weaker the mutual interaction.…”