An FPGA-based Pentium® in a complete desktop system

Lu, Shih-Lien; Yiannacouras, Peter; Kassa, Rolf; Konow, Michael; Suh, Taeweon

doi:10.1145/1216919.1216927

Cited by 31 publications

(16 citation statements)

References 8 publications

(5 reference statements)

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“…Power consumption is not currently the dominant design constraint due to lower clock speeds, while area is often the primary constraint due to high area overheads of FPGA circuits. Characteristics such as inefficient multiplexers and the need to map RAM structures into FPGA hard SRAM blocks are known and generally adjusted for by modifying circuit-level, but not microarchitecture-level, design [8][9][10][11].…”

Section: Technology Impact On Microarchitecturementioning

confidence: 99%

Comparing FPGA vs. custom cmos and the impact on processor microarchitecture

Wong

Betz

Rose

2011

Proceedings of the 19th ACM/SIGDA International Symposium on Field Programmable Gate Arrays

100

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As soft processors are increasingly used in diverse applications, there is a need to evolve their microarchitectures in a way that suits the FPGA implementation substrate. This paper compares the delay and area of a comprehensive set of processor building block circuits when implemented on custom CMOS and FPGA substrates. We then use the results of these comparisons to infer how the microarchitecture of soft processors on FPGAs should be different from hard processors on custom CMOS.We find that the ratios of the area required by an FPGA to that of custom CMOS for different building blocks varies significantly more than the speed ratios. As area is often a key design constraint in FPGA circuits, area ratios have the most impact on microarchitecture choices. Complete processor cores have area ratios of 17-27× and delay ratios of 18-26×. Building blocks that have dedicated hardware support on FPGAs such as SRAMs, adders, and multipliers are particularly area-efficient (2-7× area ratio), while multiplexers and CAMs are particularly area-inefficient (> 100× area ratio), leading to cheaper ALUs, larger caches of low associativity, and more expensive bypass networks than on similar hard processors. We also find that a low delay ratio for pipeline latches (12-19×) suggests soft processors should have pipeline depths 20% greater than hard processors of similar complexity.

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Section: Technology Impact On Microarchitecturementioning

confidence: 99%

Comparing FPGA vs. custom cmos and the impact on processor microarchitecture

Wong

Betz

Rose

2011

Proceedings of the 19th ACM/SIGDA International Symposium on Field Programmable Gate Arrays

100

View full text Add to dashboard Cite

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“…These designs offer increased parallelism, typically up to about 4 functional units. FPGAs have also been used to prototype VLIW and superscalar architectures intended for full-custom implementation, but they tend to be inefficient in area and performance [Lu et al 2007;Ray and Hoe 2003]. …”

Section: Soft Processormentioning

confidence: 99%

Vector Processing as a Soft Processor Accelerator

Eagleston

Chou

et al. 2009

ACM Trans. Reconfigurable Technol. Syst.

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Current FPGA soft processor systems use dedicated hardware modules or accelerators to speed up data-parallel applications. This work explores an alternative approach of using a soft vector processor as a general-purpose accelerator. The approach has the benefits of a purely softwareoriented development model, a fixed ISA allowing parallel software and hardware development, a single accelerator that can accelerate multiple applications, and scalable performance from the same source code. With no hardware design experience needed, a software programmer can make area-versus-performance tradeoffs by scaling the number of functional units and register file bandwidth with a single parameter. A soft vector processor can be further customized by a number of secondary parameters to add or remove features for a specific application to optimize resource utilization. This paper introduces VIPERS, a soft vector processor architecture that maps efficiently into an FPGA and provides a scalable amount of performance for a reasonable amount of area. Compared to a Nios II/s processor, instances of VIPERS with 32 processing lanes achieve up to 44× speedup using up to 26× the area.

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“…Recent FPGA efforts such as Lu et al [2007] and Vahia and Hartke [2007] have produced full-system prototypes involving a CPU implemented in an FPGA, while real motherboards and PC components are used to provide the CPU-external full-system environment. In both examples, the CPU designs are commandeered from existing RTL models developed originally for standard cell technologies.…”

Section: Related Workmentioning

confidence: 99%

ProtoFlex

Chung

Papamichael

Nurvitadhi

et al. 2009

ACM Trans. Reconfigurable Technol. Syst.

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Functional full-system simulators are powerful and versatile research tools for accelerating architectural exploration and advanced software development. Their main shortcoming is limited throughput when simulating large multiprocessor systems with hundreds or thousands of processors or when instrumentation is introduced. We propose the PROTOFLEX simulation architecture, which uses FPGAs to accelerate full-system multiprocessor simulation and to facilitate high-performance instrumentation. Prior FPGA approaches that prototype a complete system in hardware are either too complex when scaling to large-scale configurations or require significant effort to provide full-system support. In contrast, PROTOFLEX virtualizes the execution of many logical processors onto a consolidated number of multiple-context execution engines on the FPGA. Through virtualization, the number of engines can be judiciously scaled, as needed, to deliver on necessary simulation performance at a large savings in complexity. Further, to achieve low-complexity full-system support, a hybrid simulation technique called transplanting allows implementing in the FPGA only the frequently encountered behaviors, while a software simulator preserves the abstraction of a complete system.We have created a first instance of the PROTOFLEX simulation architecture, which is an FPGAbased, full-system functional simulator for a 16-way UltraSPARC III symmetric multiprocessor server, hosted on a single Xilinx Virtex-II XCV2P70 FPGA. On average, the simulator achieves a 38x speedup (and as high as 49×) over comparable software simulation across a suite of applications, including OLTP on a commercial database server. We also demonstrate the advantages of Funding for this work was provided in part by grants from the C2S2 Marco Center, NSF CCF-0811702, NSF CNS-0509356, and SUN. This work was also supported by donations from Xilinx and Bluespec. Authors' addresses: E. S. Chung, M. K. Papamichael, E. Nurvitadhi, J. C. Hoe, and K. Mai, Computer Architecture Laboratory at Carnegie Mellon, 5000 Forbes Ave., Pittsburgh, PA 15213; email: echung@ece.cmu.edu; B. Falsafi, Parallel Systems Architecture Laboratory,École Polytechnique Fédérale de Lausanne, Lausanne, Switzerland. Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or direct commercial advantage and that copies show this notice on the first page or initial screen of a display along with the full citation. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, to republish, to post on servers, to redistribute to lists, or to use any component of this work in other works requires prior specific permission and/or a fee. Permissions may be requested from Publications Dept., ACM, Inc., 2 Penn Plaza, Suite 701, New York, NY 10121-0701 USA, fax +1 (212)

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An FPGA-based Pentium® in a complete desktop system

Cited by 31 publications

References 8 publications

Comparing FPGA vs. custom cmos and the impact on processor microarchitecture

Comparing FPGA vs. custom cmos and the impact on processor microarchitecture

Vector Processing as a Soft Processor Accelerator

ProtoFlex

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