An FPGA based high speed IEEE-754 double precision floating point multiplier using Verilog

FPGA-based Low Latency Inverse QRD Architecture for Adaptive Beamforming in Phased Array Radars

“…Many researchers also performed a lot of work in single precision floating point multiplier which is also a complex mathematical operation in hardware [23][24][25], but we keep our focus in divider and square-root operations and use the multiplier core of the FPGA. Xilinx Virtex 5 FPGA is the selected platform for hardware implementation.…”

Comparative Review of Floating-Point Multiplier Systems

“…[20] also claimed that the use of the self-timed floating-point multiplier developed resulted in a 20% improvement in power consumption when compared to the synchronous multiplier implementation. [23] presented the implementation of high speed floating-point double-precision multiplier which is compliant with the IEEE 754 standard for floating-point numbers, hence handling overflow, underflow and rounding conditions. The system of [23] computed the biased exponent by the summation of both biased exponents of inputs using binary adders followed by subtraction of the bias.…”

“…[23] presented the implementation of high speed floating-point double-precision multiplier which is compliant with the IEEE 754 standard for floating-point numbers, hence handling overflow, underflow and rounding conditions. The system of [23] computed the biased exponent by the summation of both biased exponents of inputs using binary adders followed by subtraction of the bias. [23] broke up the input mantissa bits into ten (10) parts, partial products were generated, after which partial products were summed together.…”

“…The system of [23] computed the biased exponent by the summation of both biased exponents of inputs using binary adders followed by subtraction of the bias. [23] broke up the input mantissa bits into ten (10) parts, partial products were generated, after which partial products were summed together. The system of [23] was implemented on the Virtex-6 xc6vlx75t-3ff484 using Xilinx ISE 12.1i.…”

“…[23] broke up the input mantissa bits into ten (10) parts, partial products were generated, after which partial products were summed together. The system of [23] was implemented on the Virtex-6 xc6vlx75t-3ff484 using Xilinx ISE 12.1i. The system was simulated using Modelsim 6.6c.…”