An FPGA based 1.6 GHz cross-correlator for synthetic aperture interferometric radiometer

Asif, Muhammad; Guo, Xiangzhou; Zhang, Jing; Miao, Jungang

doi:10.1109/piers-fall.2017.8293294

Cited by 7 publications

(6 citation statements)

References 16 publications

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“…It can safely be assumed that this correlator can perform well at 250 MHz resulting in a collective capacity of 2 GHz from all 8 lanes. This is where our proposed design partition technique for correlator implementation proved fruitful, as our first design without this partition could only run at 200 MHz giving a total of 1.6 GHz throughput as described in [ 26 ]. Device view shows that the correlation and first stage integration modules, running at higher frequency, were implemented using resources with minimum physical separation while the modules containing second stage of integration were implemented using device resources scattered over comparatively large area owing to the fixed location of BRAM and DSP slices.…”

Section: Design Verification and Resultsmentioning

confidence: 99%

“…The difference from [ 7 , 19 ] is that they implemented the first stage as a pre-scaler which is not a part of readout values, while we have implemented it as two stage accumulation. The idea of design partition in low-speed and high speed clock domains arisen from our baseline implementation [ 26 ] where all the correlation and accumulation operations are carried out on the same, high-speed clock. It was observed that all the critical paths existed between the first stage integrator and the second stage, where signals from 256 first stage integrators were being accumulated by a pair of an adder and a DPRAM.…”

Section: Correlation System Designmentioning

confidence: 99%

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Frequency Based Design Partitioning to Achieve Higher Throughput in Digital Cross Correlator for Aperture Synthesis Passive MMW Imager

Asif

Guo

Zhang

et al. 2018

Sensors

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Digital cross-correlation is central to many applications including but not limited to Digital Image Processing, Satellite Navigation and Remote Sensing. With recent advancements in digital technology, the computational demands of such applications have increased enormously. In this paper we are presenting a high throughput digital cross correlator, capable of processing 1-bit digitized stream, at the rate of up to 2 GHz, simultaneously on 64 channels i.e., approximately 4 Trillion correlation and accumulation operations per second. In order to achieve higher throughput, we have focused on frequency based partitioning of our design and tried to minimize and localize high frequency operations. This correlator is designed for a Passive Millimeter Wave Imager intended for the detection of contraband items concealed on human body. The goals are to increase the system bandwidth, achieve video rate imaging, improve sensitivity and reduce the size. Design methodology is detailed in subsequent sections, elaborating the techniques enabling high throughput. The design is verified for Xilinx Kintex UltraScale device in simulation and the implementation results are given in terms of device utilization and power consumption estimates. Our results show considerable improvements in throughput as compared to our baseline design, while the correlator successfully meets the functional requirements.

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Section: Design Verification and Resultsmentioning

confidence: 99%

Section: Correlation System Designmentioning

confidence: 99%

Frequency Based Design Partitioning to Achieve Higher Throughput in Digital Cross Correlator for Aperture Synthesis Passive MMW Imager

Asif

Guo

Zhang

et al. 2018

Sensors

Self Cite

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“…Hardware correlators have been developed using field-programmable gate array technology to address the need. For example, multi-channel FPGA cross-correlators were used in aperture synthesis imaging systems [15][16][17]. The FPGA correlator alleviated the computational load in realtime ultrasound sensor systems using the complementary ultrasound pulse sequences for the enhancement of the signal-to-noise ratio [18].…”

Section: Introductionmentioning

confidence: 99%

FPGA Correlator for Applications in Embedded Smart Devices

Moore¹,

Lin²

2022

Biosensors

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Correlation has a variety of applications that require signal processing. However, it is computationally intensive, and software correlators require high-performance processors for real-time data analysis. This is a challenge for embedded devices because of the limitation of computing resources. Hardware correlators that use Field Programmable Gate Array (FPGA) technology can significantly boost computational power and bridge the gap between the need for high-performance computing and the limited processing power available in embedded devices. This paper presents a detailed FPGA-based correlator design at the register level along with the open-source Very High-Speed Integrated Circuit Hardware Description Language (VHDL) code. It includes base modules for linear and multi-tau correlators of varying sizes. Every module implements a simple and unified data interface for easy integration with standard and publicly available FPGA modules. Eighty-lag linear and multi-tau correlators were built for validation of the design. Three input data sets—constant signal, pulse signal, and sine signal—were used to test the accuracy of the correlators. The results from the FPGA correlators were compared against the outputs of equivalent software correlators and validated with the corresponding theoretical values. The FPGA correlators returned results identical to those from the software references for all tested data sets and were proven to be equivalent to their software counterparts. Their computation speed is at least 85,000 times faster than the software correlators running on a Xilinx MicroBlaze processor. The FPGA correlator can be easily implemented, especially on System on a Chip (SoC) integrated circuits that have processor cores and FPGA fabric. It is the ideal component for device-on-chip solutions in biosensing.

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“…Several studies show that the back-end processing system is one of the largest contributors in the power consumption of a radiometer mounted on unmanned aerial vehicles (UAVs) [6] [7][8] [9]. Most of these works used microprocessors and FPGAs to process the radiometric data, or data-loggers to store the raw data in flight and process the data on ground after the flight.…”

Section: Introductionmentioning

confidence: 99%

“…Most of these works used microprocessors and FPGAs to process the radiometric data, or data-loggers to store the raw data in flight and process the data on ground after the flight. For example, in [7] the authors use an FPGA to process the radiometric data and the power consumption was higher than 8 W. These works do not take into consideration how the power consumption of the back-end processing system impacts the performance, flight time, battery capacity, weight, and size of the radiometer.…”

Section: Introductionmentioning

confidence: 99%

A Power and Performance Study of CompactL-Band Total Power Radiometers for UAV Remote Sensing Based in the Processing on ZYNQ and ARM Architectures

Romo¹,

Rodríguez-Solís²,

Reyes³

et al. 2022

IEEE J. Sel. Top. Appl. Earth Observations Remote Sensing

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This paper presents a study on the power consumption and performance analysis of a small, portable, and ultra-low power total power L-band radiometer. The study explores two processing architectures: the ZYNQ 7010 and the ARM A8 embedded microprocessor. The processing algorithm based in C++ was tested for different clock frequencies, ADC sampling speeds, and sizes of the ADC buffer. To reduce the power consumption and the algorithm execution time, high-level and system-level optimizations, along with fixed-point Q(16,16) data representation, were applied to the main code running on LINUX Debian V8. In the case with the ZYNQ 7010, the optimizations had no notable impact on reducing power or execution time in comparison with the ARM A8, where significant variations were measured, showing a tradeoff between power consumption and algorithm performance that limits the processing capability and the system flight time. The ZYNQ 7010 runs the algorithm faster, but the power consumption is higher than the ARM A8. Using the fixed-point Q(16,16) implementation reduced the power consumption and the execution time in both architectures.Based on these results, we developed a heuristic methodology to minimize power consumption and increase the performance. Energy consumption savings for the radiometer during 20 minutes of flight was 48%. The size of the radiometer was reduced to 30cm x 30cm x 10cm, with a weight of 1.36 kg, (3 lb) allowing the system be carried by small drones. The results were validated measuring salinity at two locations in Western Puerto Rico.

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An FPGA based 1.6 GHz cross-correlator for synthetic aperture interferometric radiometer

Cited by 7 publications

References 16 publications

Frequency Based Design Partitioning to Achieve Higher Throughput in Digital Cross Correlator for Aperture Synthesis Passive MMW Imager

Frequency Based Design Partitioning to Achieve Higher Throughput in Digital Cross Correlator for Aperture Synthesis Passive MMW Imager

FPGA Correlator for Applications in Embedded Smart Devices

A Power and Performance Study of CompactL-Band Total Power Radiometers for UAV Remote Sensing Based in the Processing on ZYNQ and ARM Architectures

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