An Extrinsic Function-Level Evolvable Hardware Approach

Kalganova, Tatiana

doi:10.1007/978-3-540-46239-2_5

Cited by 24 publications

(20 citation statements)

References 10 publications

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“…Various alternatives may be found in the literature including Function-level Evolution [30,48], Increased Complexity Evolution [49,50] and Bidirectional Evolution [51].…”

Section: Divide and Conquermentioning

confidence: 98%

Challenges of evolvable hardware: past, present and the path to a promising future

Haddow

Tyrrell

2011

Genet Program Evolvable Mach

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Nature is phenomenal. The achievements in, for example, evolution are everywhere to be seen: complexity, resilience, inventive solutions and beauty. Evolvable Hardware (EH) is a field of evolutionary computation (EC) that focuses on the embodiment of evolution in a physical media. If EH could achieve even a small step in natural evolution's achievements, it would be a significant step for hardware designers. Before the field of EH began, EC had already shown artificial evolution to be a highly competitive problem solver. EH thus started off as a new and exciting field with much promise. It seemed only a matter of time before researchers would find ways to convert such techniques into hardware problem solvers and further refine the techniques to achieve systems that were competitive with or better than human designs. However, 15 years on-it appears that problems solved by EH are only of the size and complexity of that achievable in EC 15 years ago and seldom compete with traditional designs. A critical review of the field is presented. Whilst highlighting some of the successes, it also considers why the field is far from reaching these goals. The paper further redefines the field and speculates where the field should go in the next 10 years.

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“…Various alternatives may be found in the literature including Function-level Evolution [30,48], Increased Complexity Evolution [49,50] and Bidirectional Evolution [51].…”

Section: Divide and Conquermentioning

confidence: 98%

Challenges of evolvable hardware: past, present and the path to a promising future

Haddow

Tyrrell

2011

Genet Program Evolvable Mach

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“…La síntesis booleana es una herramienta útil en el diseño de hardware evolutivo (HE), pero presenta problemas si su implementación es onchip, dado que la carga computacional requerida para un algoritmo evolutivo aplicado a la síntesis booleana puede ser alta como lo demuestra Stoica [6,7], lo que representa una dificultad a la hora de ser desarrollados en sistemas embebidos. Hay implementaciones relacionadas con la síntesis booleana mediante algoritmos genéticos (AG) y programación genética (PG) realizados de forma intrínseca por Thompson [8] y extrínseca Kalganova [9] pero con un número muy reducido de variables (cuatro variables), orientados a obtener estructuras distintas de componentes básicos y donde se proponen plataformas de hardware y software para el desarrollo del algoritmo evolutivo. También se han hecho esfuerzos por aumentar las restricciones de la síntesis y aumentar el número de variables mediante su desarrollo en sistemas paralelos, con AG como lo presentan Higuchi y Manderick [10] o programación genética descrita en Cheang, Lee y Leung [3] y Chang, Hou y Su [11] proponiendo siempre arquitecturas de hardware y distintas representaciones de redes booleanas.…”

Section: Síntesis Booleana Con Aeunclassified

Síntesis booleana con programación genética paralela en CPU y GPU

Pedraza¹,

Oyaga²,

Gómez³

2013

Ingenium Rev. fac. ing.

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ResumenLa síntesis booleana o combinacional es un proceso mediante el cual se optimiza una red de puertas lógicas, con el fin de reducir su consumo, minimizar costos, minimizar área y aumentar el rendimiento a la hora de ser implementada. Por otra parte, la programación genética es una alternativa importante para generar estructuras de hardware interesantes y eficientes. Se ha demostrado que los algoritmos evolutivos (AE) tienen mejor rendimiento si se implementan en sistemas paralelos. Este artículo presenta la implementación de un algoritmo genético paralelo (PGP) para realizar síntesis booleana en una plataforma basada en CPU-GPU. Esta implementación emplea el modelo de islas, el cual permite la evolución paralela e independiente del PGP a través de las múltiples unidades de procesamiento de la GPU y los múltiples núcleos de un procesador de última generación. Se probaron diferentes alternativas de mapeo del PGP en la plataforma en orden de optimizar el tiempo de respuesta. Como resultado se muestra una aceleración superior a 41. Palabras claveProgramación paralela, síntesis booleana, GPU, algoritmo evolutivo.

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“…However, one of the main weaknesses of this approach is that it still requires human intervention to select the most appropriate functions for specific problems. Function-level evolution has been further extended in [67]. Although the proposed approach significantly reduces the number of generations required to obtain a fully functional solution, the evolvability [46], [48], [49] of logic circuits with a higher number of inputs remains the central issue.…”

Section: Scalability Problems and Stalling Effect In The Fitness mentioning

confidence: 99%

Generalized Disjunction Decomposition for Evolvable Hardware

Stomeo¹,

Kalganova²,

Lambert³

2006

IEEE Trans. Syst., Man, Cybern. B

102

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Abstract-Evolvable hardware (EHW) refers to selfreconfiguration hardware design, where the configuration is under the control of an evolutionary algorithm (EA). One of the main difficulties in using EHW to solve real-world problems is scalability, which limits the size of the circuit that may be evolved. This paper outlines a new type of decomposition strategy for EHW, the "generalized disjunction decomposition" (GDD), which allows the evolution of large circuits. The proposed method has been extensively tested, not only with multipliers and parity bit problems traditionally used in the EHW community, but also with logic circuits taken from the Microelectronics Center of North Carolina (MCNC) benchmark library and randomly generated circuits. In order to achieve statistically relevant results, each analyzed logic circuit has been evolved 100 times, and the average of these results is presented and compared with other EHW techniques. This approach is necessary because of the probabilistic nature of EA; the same logic circuit may not be solved in the same way if tested several times. The proposed method has been examined in an extrinsic EHW system using the (1 + λ) evolution strategy. The results obtained demonstrate that GDD significantly improves the evolution of logic circuits in terms of the number of generations, reduces computational time as it is able to reduce the required time for a single iteration of the EA, and enables the evolution of larger circuits never before evolved. In addition to the proposed method, a short overview of EHW systems together with the most recent applications in electrical circuit design is provided.Index Terms-Adaptive system, evolutionary computation, evolvable hardware (EHW), problem decomposition.

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An Extrinsic Function-Level Evolvable Hardware Approach

Cited by 24 publications

References 10 publications

Challenges of evolvable hardware: past, present and the path to a promising future

Challenges of evolvable hardware: past, present and the path to a promising future

Síntesis booleana con programación genética paralela en CPU y GPU

Generalized Disjunction Decomposition for Evolvable Hardware

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