Generalized Disjunction Decomposition for Evolvable Hardware

Abstract

Abstract-Evolvable hardware (EHW) refers to selfreconfiguration hardware design, where the configuration is under the control of an evolutionary algorithm (EA). One of the main difficulties in using EHW to solve real-world problems is scalability, which limits the size of the circuit that may be evolved. This paper outlines a new type of decomposition strategy for EHW, the "generalized disjunction decomposition" (GDD), which allows the evolution of large circuits. The proposed method has been extensively tested, not only with multipliers and parity bit problems traditionally used in the EHW community, but also with logic circuits taken from the Microelectronics Center of North Carolina (MCNC) benchmark library and randomly generated circuits. In order to achieve statistically relevant results, each analyzed logic circuit has been evolved 100 times, and the average of these results is presented and compared with other EHW techniques. This approach is necessary because of the probabilistic nature of EA; the same logic circuit may not be solved in the same way if tested several times. The proposed method has been examined in an extrinsic EHW system using the (1 + λ) evolution strategy. The results obtained demonstrate that GDD significantly improves the evolution of logic circuits in terms of the number of generations, reduces computational time as it is able to reduce the required time for a single iteration of the EA, and enables the evolution of larger circuits never before evolved. In addition to the proposed method, a short overview of EHW systems together with the most recent applications in electrical circuit design is provided.Index Terms-Adaptive system, evolutionary computation, evolvable hardware (EHW), problem decomposition.

A Novel Genetic Algorithm for Evolvable Hardware

“…During the evaluation stage a table, called the fitness's value table, which contains the fitness's value of each chromosome that is participating in the evolution of the digital circuit, is generated (see Figure 3). The table in Figure 3 and_plane [2] chromosome of AND plane …”

“…It should be noted that the evolved logic circuits, as the 5 bit multipliers, the 5 bit adders are the most complex circuits ever evolved using a stand alone genetic algorithm. Only Stomeo in [2] was able to evolve larger circuits such as the 6 bit multiplier using the GDD for FPGA structures. A comparison with traditional synthesis approaches, which are very effective and produce impressive results, is not given since the aims of the paper are to present a new genetic algorithm applied for the evolution of combinational logic circuits, to show that is possible to have cost free design (this is because the designer should only provide the truth table of the desired circuit) and to compare the obtained designs with other automatic and self-reconfigurable methods.…”

“…HE evolutionary design of electronic circuits [1], [2] is limited by the difficulties in evolving large circuits in a reasonably short time. This is due to the scalability problems [2]- [5] and stalling effects during the fitness function calculation.…”

“…This is due to the scalability problems [2]- [5] and stalling effects during the fitness function calculation. The scalability problem limits the size of the system that may be designed using evolutionary design techniques [2]. The stalling effects appear during the evaluation of possible solutions and are as a result of the complexity of the fitness functions taken into consideration.…”

“…used during the evolution and also with the permitted connectivity between those elements. To tackle these issues and to design larger circuits, several techniques have been introduced, such as gate and function level evolution [7], increased complexity evolution [8], bi-directional incremental evolution [9], Generalized Disjunction Decomposition [2] etc. Several researchers have used different circuit structures as a base from which to evolve This work is supported in part by the EPSRC under Grant GR/S17178.…”