An experimental method to analyse trapping centres in silicon at very low concentrations

Collet, M.G.

doi:10.1016/0038-1101(75)90170-7

Cited by 17 publications

(1 citation statement)

References 9 publications

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“…The bulk trap concentration and emission krretics may be measured using a depletion-mode transistor using a technique due to Collet [1975]. The transistor is biased very close to pinch-off so that only a email current flows.…”

Section: Test Structure Measurement Proceduresmentioning

confidence: 99%

Terry-2 :

Carver¹,

Wachnik²

1984

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Capture and emis'-ion processes during charge pumping cn a p-type sub«t ''a i_e v PREFACE This work was conducted as a part of the Semiconductor Technology Program at the National Bureau of Standards (NBS).This program serves to focus NBS research to enhance the performance, interchangeability, and reliability of discrete semiconductor devices and integrated circuits through improvements in measurement technology for use in specifying materials and devices in national and international commerce and for use by industry in controlling device fabrication processes.This research leads to carefully evaluated and well-documented test procedures and associated technology. Special emphasis is placed on the dissemination of the results of the research to the electronics community. Application of these results by industry will contribute to higher yields, lower cost, and higher reliability of semiconductor devices.Improved measurement technology also leads to greater economy in government procurement by providing a common basis for the purchase specifications of government agencies and, in addition, provides a basis for controlled improvements in fabrication processes and in essential device characteristics .The segment of the Semiconductor Technology Program described in this report was supported by The Charles Stark Draper Laboratory, Inc. (CSDL) under CSDL Prime Contract N00030-81 -C-01 33 issued by the Department of the Navy, Strategic Systems Project Office. CSDL's purchase Order Number DL-H-2081 37 covered work at NBS for the period December 1, 1982 through November 30, 1983. Work was monitored by Mr. Robert E. Var of CSDL. The NBS contacts for technical information on this project are Gary P. Carver and Richard A. Wachnik of the Semiconductor Materials and Processes Division at the National Bureau of Standards, (301) 921-3786.

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Section: Test Structure Measurement Proceduresmentioning

confidence: 99%

Terry-2 :

Carver¹,

Wachnik²

1984

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Ein mögliches Modell des Stoßrauschens in pn-Übergängen

Eigler

Gaebel

1980

Phys. Stat. Sol. (a)

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P. GORLICR zum 75. Geburtstag gewidmet An npn-Planar-Epitaxie-Transistoren wird zur Ermittlung der Ursachen des StoBrauschens die Temperatur-und Spannungsabhkngigkeit des StoSrauschens beim aktiven Betrieb der Transistoren gemessen. Es wird ein Modell fiir das Stoljrauschen vorgeschlagen, nach dem die Impulsbreite durch den Einfang von Elektronen (oder Lijchern) auf Au-Niveaus bestimmt wird, die Impulspause jedoch durch Ladungstrigeremission von flacheren Niveaus, die sich dem Si-0-Si-Komplex zuordnen lassen. Es wird angenommen, daB es sich dabei um das Elektron eines Exzitons handelt, das beim Einfang durch das tieferliegende Zentrum entsteht und das durch das weniger tiefliegende Niveau eingefangen wird.

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Charge-Transfer Devices

Milnes

1980

Semiconductor Devices and Integrated Electronics

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An experimental method to analyse trapping centres in silicon at very low concentrations

Cited by 17 publications

References 9 publications

Terry-2 :

Terry-2 :

Ein mögliches Modell des Stoßrauschens in pn-Übergängen

Charge-Transfer Devices

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