An experimental 1Mb DRAM with on-chip voltage limiter

Itoh, K.; Hori, R.; Etoh, J.; Asai, S.; Hashimoto, N.; Yagi, K.; Sunami, Hideo

doi:10.1109/isscc.1984.1156686

Cited by 59 publications

(12 citation statements)

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“…This V-decoder division was applied to various sense amplifier (SA) arrangements such as one SA at each division (nor- mal arrangement) and a shared SA [9]. However, this division was almost exhausted at the 16-Mb generation with the combination of shared SA, shared I/O, and shared Y decoder, as shown in Figure 8.13 [11]. Shared I/O further divides a multi-divided data line into two, which are selected by the isolation switches, ISO and /ISO.…”

Section: Charging Capacitance Reductionmentioning

confidence: 99%

Low Power Memory Design

Itoh¹

1996

Low Power Design Methodologies

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Section: Charging Capacitance Reductionmentioning

confidence: 99%

Low Power Memory Design

Itoh¹

1996

Low Power Design Methodologies

Self Cite

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“…For higher density, main memory applications, the 1-device cell DRAM technology is used [60]. Despite this memory cell change, it is interesting to see in Figure 3 that, empirically, the performance of main memory chips follows the same general performance-size trend as the SRAM chips (see Tables 7 and 8 derived from data in references [61][62][63][64][65][66][67][68][69][70][71][72][73][74]. The data points on Figure 3 represent chips announced at different times using different technologies so that an exact comparison is not possible; nevertheless, the memory access time for IGFET or bipolar technology generally increases (degrades) about 0.6 decades for every decade increase in memory capac- ity.…”

Section: Historical Backgroundmentioning

confidence: 99%

Challenges in advanced semiconductor technology for high-performance and supercomputer applications

Osburn

Reisman

1987

J Supercomput

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This article provides a review of the capabilities, future directions, and technology challenges for semiconductor chips and packages as they apply to high-performance and supercomputer applications. Semiconductor chip technology has resulted in dramatic device density improvements over the last 20 years. Scaling theory predicts that continued improvements will be possible if the technological problems associated with patterning, doping, interconnection, density, yield, and cost can be solved. The issues associated with these challenges are discussed. Finally, the packaging needs to support advanced chip technologies are reviewed.

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“…The physical contribution to V~R may be the result of the work-function difference between the gate electrode material and silicon (r as well as the fixed surface charge density (Qss) V~B = r --eoxQ~tox [1] %x: permittivity of gate oxide (F/cm). The V~B of W gate capacitors is shown as a function of to~ in Fig.…”

Section: Reliability Of Mos Characteristicsmentioning

confidence: 99%

Fabrication of Highly Reliable Tungsten Gate MOS VLSI's

Yamamoto

Kume

Iwata

et al. 1986

J. Electrochem. Soc.

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Recently, refractory metals, such as W and Mo, with low resistivity and a high melting point have received keen interest as materials for gate electrodes and interconnects for MOS VLSI's. However, it is commonly believed that MOS devices with refractory metal gates have low reliability due to mobile ion contamination. In this work, it was clarified that W gates with commercially available W sputtering targets introduced high level mobile charges into the gate oxide. It was also found that the rates of degradation of W gate MOS transistors due to hot carriers were higher than those of poly-Si gates, and the internal stresses in W gates increased the degradation rates. Therefore, the authors developed a high purity W sputtering target fabrication technique through the use of electron melting. A W gate annealing technique was developed to reduce the internal stress in W films. Through these techniques, the above-mentioned problems can be eliminated, and W gate devices that have characteristics comparable to those of poly-Si gates can be produced.The minimum feature size of very large-scale integrated circuits (VLSI's) has been reduced to one micrometer or even less, while at the same time the number of elements per chip continues to increase. Under the present D-RAM developmental situation, a 256kb D-RAM has reached the stage of practical use, and iMb D-RAM prototypes have been examined and tested by a number of LSI makers (1-3). These developments have imposed severe demands on the materials and interconnects in MOS VLSrs.The technical and material outlook for gate electrodes and interconnects of future generation MOS VLSI's is shown in Fig. i. Polycrystalline silicon is widely used in MOS VLSI's. However, its high resistivity causes degradation in circuit speed due to R-C delay time. If poly-Si is used as a word line of a 256kb or IMb D-RAM, the delay time at the word line increases at a rapid rate.Gate electrodes and interconnects made of silicides of refractory metals (4) or their "polycides'" (5, 6) have attracted more and more interest over the past few years.However, it is apparent that the signal delay caused by the resistance they exhibit will become a serious problem in Mb-leve] VLSI's, even in silicide gates. Thus, pure metals such as Mo and W are being considered as materials for MOS gates. A new process for W gate MOS has been developed (7-9), which makes W attractive for VLSI application. For practical applications, the process using W must be reliable and the MOS characteristics must be stable over a long period of time. In this paper, problems with regard to fabrication processes or MOS characteristic reliability are discussed, and the solutions to the problems are presented. Major Problems of Tungsten GatesRefractory metals, such as W and Mo, as alternative materials for lowresistance gate electrodes, have been considered many times over the past years. However, many important problems have been left unsolved. The first of these is that W films peel off SiO2 during the patterning processes for gate ...

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An experimental 1Mb DRAM with on-chip voltage limiter

Cited by 59 publications

References 1 publication

Low Power Memory Design

Low Power Memory Design

Challenges in advanced semiconductor technology for high-performance and supercomputer applications

Fabrication of Highly Reliable Tungsten Gate MOS VLSI's

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