2016
DOI: 10.1016/j.vlsi.2015.07.001
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An exact algorithm for wirelength optimal placements in VLSI design

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Cited by 25 publications
(9 citation statements)
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“…1, we can see that BO performs competitively with only 520 evaluations of the objective on apte which is the smallest problem. We acknowledge that on the designs with a larger number of macros, ami33 and ami49, there is a non-negligible gap between BO and eWL (Funke et al, 2016). However, we expect that this gap does not translate to the real world applications that we envision since eWL cannot optimize macro placements with standard cells, while BO and SA can.…”
Section: Methodsmentioning
confidence: 97%
“…1, we can see that BO performs competitively with only 520 evaluations of the objective on apte which is the smallest problem. We acknowledge that on the designs with a larger number of macros, ami33 and ami49, there is a non-negligible gap between BO and eWL (Funke et al, 2016). However, we expect that this gap does not translate to the real world applications that we envision since eWL cannot optimize macro placements with standard cells, while BO and SA can.…”
Section: Methodsmentioning
confidence: 97%
“…Because of element size and signal delay reduction, over 80% of the total time delay now corresponds to interconnection delays. In this context, placement is becoming increasingly important, and new methods are required [14,15].…”
Section: Literature Reviewmentioning
confidence: 99%
“…In CFL problems, there is no limitation for the choice of locations, and facilities are represented by rectangles. CFLs have been used on various problems, such as finding layout of temporary buildings on a construction site (Kumar and Cheng, 2015) and designing hospitals (Hahn and Krarup, 2001) and developing microprocessor layouts (Funke et al , 2016). If material handlings are performed via halls, orthogonal linear distance is used.…”
Section: Related Literaturementioning
confidence: 99%