An error-correcting 14b/20 µ s CMOS A/D converter

Boyacigiller, Z.; Weir, B. E.; Bradshaw, Peter

doi:10.1109/isscc.1981.1156178

Cited by 36 publications

(26 citation statements)

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“…Here primary plate of bridge capacitor is joined to secondary DAC, such that the linearity error occurred due to parasitic can be minimized. To enable the ADC for correcting under approximation and over approximation decision errors , it is required that the decision levels are shifted to middle of redundancy stage [6], [7].For shifting the level, an additional capacitor is used besides the main capacitance array [5].A new approach is introduced in which decision bit and lower weighted bit are switched simultaneously [8], [9].Once the decision is happened, lower order bit is turn downed to its original state. The secondary bit has a weight equal to the redundancy of decision bit.…”

Section: Proposed Architectural Implementation Of Sar-adcmentioning

confidence: 99%

A 14-bit 10kS/s power efficient 65nm SAR ADC for cardiac implantable medical devices

Dastagiri¹,

Kishore²

2018

IJET

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This brief presents a 10kS/s 14 bit 12.5 ENOB Successive Approximation Register Analog-to-Digital Converter for Cardiac Implantable Medical. For achieving power efficient operation, SAR ADC employ SAR control, a new power and noise efficient comparator topology, non-binary weighted capacitive DAC. The linearity of implemented SAR ADC is enhanced with the uniform geometry of non-binary weighted capacitive DAC.The proposed SAR ADC is implemented using 65nm CMOS technology. The latched comparator consumes a power of 2.4uW and it provides an ENOB of 12.6 at a supply voltage of 1V.The INL is between -2.7/+1.6 LSB and DNL is between -0.6/+1.4LSB. The FOM of ADC is 40fJ/conv.Step which is comparable with existing ADC topologies.

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Section: Proposed Architectural Implementation Of Sar-adcmentioning

confidence: 99%

A 14-bit 10kS/s power efficient 65nm SAR ADC for cardiac implantable medical devices

Dastagiri¹,

Kishore²

2018

IJET

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“…Hence, it is important to shift the comparison threshold during the bit decision to the middle of the redundancy range [7], [9]. One way is to tie an extra capacitor bank to the original array and to increase the comparison threshold by switching on an additional capacitor together with the decision capacitor [7].…”

Section: Secondary Bit To Tackle One-side Redundancymentioning

confidence: 99%

“…One way is to tie an extra capacitor bank to the original array and to increase the comparison threshold by switching on an additional capacitor together with the decision capacitor [7]. A more efficient approach is to simultaneously switch on two bits [9], in which one bit is the decision bit and the other is a lower weighted bit. The secondary bit has a weight about half of the redundancy.…”

Section: Secondary Bit To Tackle One-side Redundancymentioning

confidence: 99%

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Analysis and Calibration of Nonbinary-Weighted Capacitive DAC for High-Resolution SAR ADCs

Zhang

Alvandpour

2014

IEEE Trans. Circuits Syst. II

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Abstract-This brief analyzes the effect of capacitor variation on the design of high-resolution nonbinary-weighted successiveapproximation-register analog-to-digital converters in terms of radix, conversion steps, and accuracy. Moreover, the limitation caused by the one-side redundancy of the nonbinary-weighted network is addressed and a corresponding solution with a mathematical derivation is provided. In order to relax the mismatch requirement on the capacitor sizing while still ensuring enough linearity, a bottom-up weight calibration technique accounting for noise and offset errors is proposed, and its effectiveness is demonstrated. This calibration approach can be easily incorporated into a charge-redistribution converter without modifying its main architecture and conversion sequence.Index Terms-Capacitor variation, digital error correction, nonbinary weighted, redundancy, successive approximation, successive approximation register (SAR) analog-to-digital converters (ADCs), weight calibration.

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“…It limits the ability of the ADC in correcting early decision errors due to insufficient settling or coupled noise by later decision steps. To solve this problem, a solution briefly mentioned in [62] is introduced, and a mathematical derivation of the solution is further provided.…”

Section: Introductionmentioning

confidence: 99%

Ultra-Low-Power Analog-to-Digital Converters for Medical Applications

Zhang

2014

Linköping Studies in Science and Technology. Dissertations

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Biomedical systems are commonly attached to or implanted into human bodies, and powered by harvested energy or small batteries. In these systems, analog-to-digital converters(ADCs) are key components as the interface between the analog world and the digital domain. Conversion of the low frequency bioelectric signals does not require high speed, but ultra-low-power operation. This combined with the required conversion accuracy makes the design of such ADCs a major challenge. Among prevalent ADC architectures, the successive-approximation-register (SAR) ADC exhibits significantly high energy efficiency due to its good trade-offs among power consumption, conversion accuracy, and design complexity. This thesis examines the physical limitations and investigates the design methodologies and circuit techniques for low-speed and ultra-low-power SAR ADCs.The power consumption of SAR ADC is analyzed and its lower bounds are formulated in the thesis. At low resolutions, power is bounded by minimum feature sizes; while at medium to high resolutions, power is bounded by thermal noise and capacitor mismatch. In order to relax the mismatch requirement on the capacitor sizing while still ensuring enough linearity for high resolution, a bottom-up weight calibration technique is further proposed. It utilizes redundancy generated by a non-binary-weighted capacitive network, and measures the actual weights of more significant capacitors using less significant capacitors.Three SAR ADCs have been implemented. The first ADC, fabricated in a 0.13µm CMOS process, achieves 9.1ENOB with 53-nW power consumption at 1kS/s. The main key to achieve the ultra-low-power operation turns out to be the maximal simplicity in the ADC architecture and low transistor count. In addition, a dual-supply voltage scheme allows the SAR digital logic to operate at 0.4V, reducing the overall power consumption of the ADC by 15% without any loss in performance. Based on the understanding from the first ADC and motivated by the predicted power bounds, the second ADC, a single-supply 9.1-ENOB SAR ADC in 65nm CMOS process has been further fabricated. It achieves a substantial (94%) improvement in power consumption with 3-nW total power at 1kS/s and 0.7V. Following the same concept of imposing maximal simplicity in the ADC architecture and taking advantage of the smaller feature size, the ultra-low-power consumption is achieved by a matched splitiv array capacitive DAC, a bottom-plate full-range input-sampling scheme, a latch-based SAR control logic, and a multi-V T design approach. The third ADC fabricated in 65nm CMOS process targets at a higher resolution of 14b and a wider bandwidth of 5KHz. It achieves 12.5ENOB with 1.98-µW power consumption at 0.8V and 10kS/s. To achieve the high resolution, the ADC implements a uniform-geometry non-binaryweighted capacitive DAC and employs a secondary-bit approach to dynamically shift decision levels for error correction. Moreover, a comparator with bias control utilizes the redundancy to reduce the power consumption....

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An error-correcting 14b/20 µ s CMOS A/D converter

Cited by 36 publications

References 0 publications

A 14-bit 10kS/s power efficient 65nm SAR ADC for cardiac implantable medical devices

A 14-bit 10kS/s power efficient 65nm SAR ADC for cardiac implantable medical devices

Analysis and Calibration of Nonbinary-Weighted Capacitive DAC for High-Resolution SAR ADCs

Ultra-Low-Power Analog-to-Digital Converters for Medical Applications

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