An enhanced cut-points algorithm in formal equivalence verification

Khasidashvili, Zurab; Moondanos, John; Kaiss, Daher; Hanna, Ziyad

doi:10.1109/hldvt.2001.972825

Cited by 11 publications

(5 citation statements)

References 5 publications

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“…We are also planing to investigate if simulation distances [10] can be used to find a semantically close repair. Finally, we are planing to continue our experiments with model checkers specialized in solving the sequential equivalence checking problem [28,29]. We believe that such solvers perform well on our problem, because M and M have many similar structures.…”

Section: Resultsmentioning

confidence: 97%

Program repair without regret

Essen

Jobstmann

2015

Form Methods Syst Des

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We present a new and flexible approach to repair reactive programs with respect to a specification. The specification is given in linear-temporal logic. Like in previous approaches, we aim for a repaired program that satisfies the specification and is syntactically close to the faulty program. The novelty of our approach is that it produces a program that is also semantically close to the original program by enforcing that a subset of the original traces is preserved. Intuitively, the faulty program is considered to be a part of the specification, which enables us to synthesize meaningful repairs, even for incomplete specifications. Our approach is based on synthesizing a program with a set of behaviors that stay within a lower and an upper bound. We provide an algorithm to decide if a program is repairable with respect to our new notion, and synthesize a repair if one exists. We analyze several ways to choose the set of traces to leave intact and show the boundaries they impose on repairability. We also discuss alternative notions based on reward models to obtain repair systems that behave similar to the original system. We have evaluated the approach on several examples.

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Section: Resultsmentioning

confidence: 97%

Program repair without regret

Essen

Jobstmann

2015

Form Methods Syst Des

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“…An automatic method for invariant discovery can of course help and is compatible with our approach, but does not remove the need for verification. Our work also has a number of similarities with formal equivalence verification [15,16], but the distance between RTL and HLM is larger here.…”

Section: Resultsmentioning

confidence: 99%

Formal Verification of Pentium ® 4 Components with Symbolic Simulation and Inductive Invariants

Kaivola

2005

Computer Aided Verification

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We describe a practical methodology for large-scale formal verification of control-intensive industrial circuits. It combines symbolic simulation with human-generated inductive invariants, and a proof tool for verifying implications between constraint lists. The approach has emerged from extensive experiences in the formal verification of key parts of the Intel IA-32 Pentium 4 microprocessor designs. We discuss it the context of two case studies: Pentium 4 register renaming mechanism and BUS recycle logic.

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“…In this paper we presented FEV-Extract, which was developed as part of Intel's Formal Equivalence Verification CAD system [8,9]. We explained its working flow, its main algorithms that enable automatic identification of logical elements, its hierarchical analysis flow, and a few other innovative algorithms that overall make FEV-Extract a step function compared to other published methods in academic or in the EDA industrial world.…”

Section: Discussionmentioning

confidence: 99%

High capacity and automatic functional extraction tool for industrial VLSI circuit designs

Novakovsky

Shyman

Hanna

2002

Proceedings of the 2002 IEEE/ACM International Conference on Computer-Aided Design - ICCAD '02

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In this paper we present an advanced functional extraction tool for automatic generation of high-level RTL from switch-level circuit netlist representation. The tool is called FEV-Extract and is part of a comprehensive Formal Equivalence Verification (FEV) system developed at Intel to verify modern microprocessor designs. FEV-Extract employs a powerful hierarchical analysis procedure, and advanced and generic algorithms for automatic recognition of logical primitives, to cope with variety of circuit design styles and their complexity. Logic equations are then extracted to generate a behavioral RTL model described in industrial standard HDL languages, to be used in the formal equivalence verification, logic simulation, synthesis and testability flows.

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An enhanced cut-points algorithm in formal equivalence verification

Cited by 11 publications

References 5 publications

Program repair without regret

Program repair without regret

Formal Verification of Pentium ® 4 Components with Symbolic Simulation and Inductive Invariants

High capacity and automatic functional extraction tool for industrial VLSI circuit designs

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