An Energy-Efficient Scheme for STT-RAM L1 Cache

Ye, Jun; Ma, Jianliang; Chen, Tianzhou; Hu, Tongsen

doi:10.1109/hpcc.and.euc.2013.191

Cited by 6 publications

(5 citation statements)

References 10 publications

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“…First, relaxing the nonvolatility of STT-RAM to reduce the access latency [13], [14]. Non-volatility relaxation is achievable by reducing the MTJ planar area and MTJ switching current [20]. Second, reducing the STT-RAM's write energy consumption by reducing the number of writes to STT-RAM.…”

Section: Hca For L1 Cachesmentioning

confidence: 99%

eBaRe: An Efficient Backup and Restore Techniques in Hybrid L-1 Cache for Energy Harvesting Devices

Badri¹,

Saini²,

Goel³

2022

Preprint

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Battery operated devices are rapidly increasing due to the bulk usage of IoT enabled nodes in various fields. The alternative and promising solution to replace battery-operated devices is energy harvesters, which helps to power up the embedded devices. The energy harvester systematically stores sufficient energy in a capacitor to power up the embedded device for computing the task. This type of computation is defined as intermittent computing. Energy harvesters cannot ensure a continuous power supply for embedded devices. All registers and cache are volatile in conventional processors. We require a Non-Volatile Memory (NVM) based Non-Volatile Processor (NVP), which store the registers and cache contents during power failure. Introducing NVM at the cache level degrades the system performance and consumes more energy than SRAM based caches. In this paper, an Efficient Backup and Restore (eBaRe) hybrid cache architecture is proposed by integrating SRAM and STT-RAM at a first-level cache. The eBaRe architecture proposes cache block placement and migration policies to reduce the number of writes to STT-RAM. During a power failure, the backup strategy finds the important blocks to migrate from SRAM to STT-RAM. In comparison to baseline architecture, eBaRe architecture reduces STT-RAM writes from 63.35% to 35.93%, resulting in a 32.85% performance gain and 23.42% reduction in energy consumption. Our backup strategy decreases backup time by 34.46% compared with baseline.

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Section: Hca For L1 Cachesmentioning

confidence: 99%

eBaRe: An Efficient Backup and Restore Techniques in Hybrid L-1 Cache for Energy Harvesting Devices

Badri¹,

Saini²,

Goel³

2022

Preprint

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“…Due to their low leakage power consumption, large scale last-level caches (L2 or L3 caches) have been an attractive candidate for STT-RAM deployment [2,3,5,8]. In addition, there have been several studies that utilize STT-RAM cells for L1 cache memories [1,4,6,7]. However, those studies introduced above do not consider read disturbance of future technology STT-RAM cells.…”

Section: Related Workmentioning

confidence: 99%

“…However, a major impediment to employ STT-RAM cells in on-chip caches has been their inferior write performance and energy-efficiency compared to conventional SRAM cells. Thus, the main focus of the previous studies is to mitigate an adverse impact of write operations in STT-RAM cells deployed for on-chip caches [1,2,3,4,5,6,7,8].…”

mentioning

confidence: 99%

A novel technique for technology-scalable STT-RAM based L1 instruction cache

Kong

2016

IEICE Electron. Express

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STT-RAM is an emerging memory cell to construct on-chip memories or caches. However, in advanced process technology, it is known that STT-RAM cells are vulnerable to read disturbance. To employ STT-RAM cells in on-chip caches for better energy-and cost-efficiency, appropriate techniques to prevent or avoid read disturbance are essential. In this paper, we propose a novel architectural technique to enable an energy-and performance-efficient STT-RAM based L1 instruction caches for future process technologies. Our selective way access with a write line buffer adopts a sequential cache access between the MRU way and non-MRU way, reducing energy overhead from the data restoring after the read operation. In addition, the write line buffer hides a latency of currently pending or on-going write operations in L1 instruction caches, minimizing stalls in processor pipelines. Our proposed techniques improve performance per Watt of the STT-RAM based L1 instruction cache by 1.6X and 2.6X compared to the conventional SRAM-based cache (denoted as SRAM in this paper) and STT-RAM based cache with the naive data restoring (denoted as STTRAM_dr in this paper).

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“…In [19], an SRAM-STTRAM hybrid L1 cache design is introduced for multi-core cache coherence. For refresh energy reduction in STTRAM-based L1 caches, a 'no refresh' scheme was proposed in [9]. A compiler-assisted STTRAM-based L1 cache architecture was also proposed in [20].…”

Section: Related Workmentioning

confidence: 99%

“…It enables a deployment of the STTRAM cells in L1 caches [8,9] as it can reduce write latency as well as write energy of the STTRAM cells. Though write energy and latency of the optimized STTRAM cells are still higher than those of 6T SRAM cells, thanks to the lower read access energy and leakage power, energy consumption of the STTRAM-based L1 caches can be reduced by up to 40% with a negligible performance loss [8] compared to that of the SRAMbased L1 caches.…”

Section: Introductionmentioning

confidence: 99%

A Locality-Aware Write Filter Cache for Energy Reduction of STTRAM-Based L1 Data Cache

Kong

2016

JSTS:Journal of Semiconductor Technology and Science

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Abstract-Thanks to superior leakage energy efficiency compared to SRAM cells, STTRAM cells are considered as a promising alternative for a memory element in on-chip caches. However, the main disadvantage of STTRAM cells is high write energy and latency. In this paper, we propose a lowcost write filter (WF) cache which resides between the load/store queue and STTRAM-based L1 data cache. To maximize efficiency of the WF cache, the line allocation and access policies are optimized for reducing energy consumption of STTRAM-based L1 data cache. By efficiently filtering the write operations in the STTRAM-based L1 data cache, our proposed WF cache reduces energy consumption of the STTRAM-based L1 data cache by up to 43.0% compared to the case without the WF cache. In addition, thanks to the fast hit latency of the WF cache, it slightly improves performance by 0.2%. Index Terms-Spin torque transfer random access memory, filter cache, energy efficiency, performance, L1 data cache

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An Energy-Efficient Scheme for STT-RAM L1 Cache

Cited by 6 publications

References 10 publications

eBaRe: An Efficient Backup and Restore Techniques in Hybrid L-1 Cache for Energy Harvesting Devices

eBaRe: An Efficient Backup and Restore Techniques in Hybrid L-1 Cache for Energy Harvesting Devices

A novel technique for technology-scalable STT-RAM based L1 instruction cache

A Locality-Aware Write Filter Cache for Energy Reduction of STTRAM-Based L1 Data Cache

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