An energy-efficient reconfigurable analog-to-digital converter for orthopedic implants

A pipelined analog-to-digital converter (ADC) that exhibits both power and area e±ciencies is presented in this paper for ZigBee receiver applications. A combined opamp-and capacitorsharing technique which presents a novel method to eliminate the memory e®ect is proposed. Fabricated in a 0.13-m CMOS process, the prototype 7-bit 16-MS/s ADC occupies 0.16 mm 2 active die area and achieves 41.9 dB signal-to-noise-and-distortion ratio (SNDR), 52.1 dB spurious-free dynamic rage (SFDR). The experimental results show that the¯gure of merit (FOM) is 1.12 pJ/step and power dissipation is 1.82 mW from a 1.2 V supply.

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An energy-efficient reconfigurable analog-to-digital converter for orthopedic implants

Cited by 3 publications

References 20 publications

A low-power ADC with compact AGC loop for LR-WPAN receivers

A low-power ADC with compact AGC loop for LR-WPAN receivers

Design of a fully integrated receiver analog baseband chain for 2.4-GHz ZigBee applications

A Power-Efficient Compact Pipelined ADC for ZigBee Receiver Applications

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