An Energy-Efficient Mixed-Bit CNN Accelerator With Column Parallel Readout for ReRAM-Based In-Memory Computing

Liu, Dingbang; Zhou, Haoxiang; Mao, Wei; Li, Jun; Han, Yuanfei; Man, Changhai; Wu, Qiuping; Guo, Zhiru; Huang, Mingqiang; Luo, Shaobo; Lv, Mingsong; Chen, Quan; Yu, Hao

doi:10.1109/jetcas.2022.3212314

Cited by 7 publications

(2 citation statements)

References 36 publications

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“…In the design of approximate multipliers, PPM truncation a common technique. For example, the bandwidth of ADC in analog MAC operation determines the total bitwidth of the output data and truncates the complete output information [30], [31]. However, the number of truncated PP will cause errors, which will affect the calculation accuracy of the multiplier.…”

Section: A Truncation Error Compensationmentioning

confidence: 99%

A Low-Power DNN Accelerator With Mean-Error-Minimized Approximate Signed Multiplier

Du,

Ni,

Liu

et al. 2024

IEEE Open J. Circuits Syst.

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Approximate computing is an emerging and effective method for reducing energy consumption in digital circuits, which is critical for energy-efficient performance improvement of edge-computing devices. In this paper, we propose a low-power DNN accelerator with novel signed approximate multiplier based on probability-optimized compressor and error compensation. The probability-optimized compressor is customized for partial product matrix (PPM) of signed operands, which gets the optimal logic circuit after probabilistic analysis and optimization. At the same time, we explored the PPM truncation method, found out the impact of different partial product (PP) truncation numbers on circuit benefit and error, and achieved a more ideal performance-error tradeoff through a reasonable error compensation method. In the optimal case of 8 bits, the proposed approximate multiplier saves 49.84% power, 46.41% area and 24.65% delay compared to the exact multiplier. We employed the proposed approximate multiplier in the vector systolic array as the processing element (PE). Under the VGG-16 evaluation, the proposed accelerator achieves performance improvement of energy efficiency 1.96×, while the error loss was only 0.95%.

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Section: A Truncation Error Compensationmentioning

confidence: 99%

A Low-Power DNN Accelerator With Mean-Error-Minimized Approximate Signed Multiplier

Du,

Ni,

Liu

et al. 2024

IEEE Open J. Circuits Syst.

Self Cite

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“…Here we are designing a CNN Accelerator. A CNN (Convolutional Neural Network) accelerator [4] is a specific sort of hardware accelerator created to speed up calculations necessary for convolutional deep neural network inference and training. A frequent application of CNNs in image and video processing is the recognition of objects, the identification of faces, and the segmentation of images.…”

Section: Introductionmentioning

confidence: 99%

High speed and Area Efficient FPGA Implementation of CNN Accelerator for Biomedical Applications

P.L.,

Poola,

Yellampalli

2023

Preprint

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Hardware accelerator is a specialized hardware component created to carry out particular tasks faster than a general-purpose CPU. Its goal is to expedite particular computations or processes that a general-purpose processor cannot effectively handle due to their complexity or length. Hardware accelerators play an important role in increasing the functionality and performance of electronic gadgets by allowing them to conduct complex computations. There are variety forms of hardware accelerators such as GPU’S, FPGA, ASIC’s, TPU, DSP etc., In this paper we have designed CNN Accelerator. CNN is a special hardware accelerator for speed up the calculations which are necessary for convolutional deep neural network inference and training. The main goal of CNN Accelerator is to do the calculations and enhance the functionality and energy efficiency of deep learning systems. This uses the various architectures such as convolution, activation, pooling and fully connected layer. The main block for building this accelerator is processing element [PE]. Here we have designed new processing element block which consumes less area, low power of 15% and gives high speed of 11% when compared to the existing block. CNN Accelerator is designed with the proposed processing element block, since Accelerator deals with the speed constraint. Implementation of the CNN Accelerator is done on the Artix 7 FPGA board and this consumes the area of 7186 slices and on-chip power of 100.486W. The proposed Accelerator gives high speed than earlier designs.

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RRAM-Based Precision-Scaleable Computing-In-Memory Scheme and Its Error Correction Approach

et al. 2023

2023 IEEE 5th International Conference on Artificial Intelligence Circuits and Systems (AICAS)

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An Energy-Efficient Mixed-Bit CNN Accelerator With Column Parallel Readout for ReRAM-Based In-Memory Computing

Cited by 7 publications

References 36 publications

A Low-Power DNN Accelerator With Mean-Error-Minimized Approximate Signed Multiplier

A Low-Power DNN Accelerator With Mean-Error-Minimized Approximate Signed Multiplier

High speed and Area Efficient FPGA Implementation of CNN Accelerator for Biomedical Applications

RRAM-Based Precision-Scaleable Computing-In-Memory Scheme and Its Error Correction Approach

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