High speed and Area Efficient FPGA Implementation of CNN Accelerator for Biomedical Applications

Abstract

Hardware accelerator is a specialized hardware component created to carry out particular tasks faster than a general-purpose CPU. Its goal is to expedite particular computations or processes that a general-purpose processor cannot effectively handle due to their complexity or length. Hardware accelerators play an important role in increasing the functionality and performance of electronic gadgets by allowing them to conduct complex computations. There are variety forms of hardware accelerators such as GPU’S, FPGA, ASIC’s, TPU, DSP etc., In this paper we have designed CNN Accelerator. CNN is a special hardware accelerator for speed up the calculations which are necessary for convolutional deep neural network inference and training. The main goal of CNN Accelerator is to do the calculations and enhance the functionality and energy efficiency of deep learning systems. This uses the various architectures such as convolution, activation, pooling and fully connected layer. The main block for building this accelerator is processing element [PE]. Here we have designed new processing element block which consumes less area, low power of 15% and gives high speed of 11% when compared to the existing block. CNN Accelerator is designed with the proposed processing element block, since Accelerator deals with the speed constraint. Implementation of the CNN Accelerator is done on the Artix 7 FPGA board and this consumes the area of 7186 slices and on-chip power of 100.486W. The proposed Accelerator gives high speed than earlier designs.