An Energy-Efficient Full Adder Cell Using CNFET Technology

Reshadinezhad, Mohammad Reza; Moaiyeri, Mohammad Hossein; Navi, K.

doi:10.1587/transele.e95.c.744

Cited by 35 publications

(27 citation statements)

References 17 publications

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“…Addition/Subtraction is one of the basic structures in many VLSI systems such as microprocessors, digital computing and signal processing systems and nano-micro system [1,2]. Full adder is one of the most important units in arithmetic circuits, and its performance could affect the efficiency of the whole system [3,4,5].…”

Section: Introductionmentioning

confidence: 99%

A Novel 4×4 Universal Reversible Gate as a Cost Efficient Full Adder/Subtractor in Terms of Reversible and Quantum Metrics

Moghimi

Reshadinezhad

2015

IJMECS

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Abstract-This paper proposes a new 4×4 reversible logic gate which is named as MOG. Reversible gates are logical basic units, having equal number of input and output lines, which can reduce power dissipation in digital systems design through their reversibility feature; because there is a one-to-one corresponding between their input and outputs vectors. The most significant aspect of the MOG gate is that it is a universal gate and has the ability of calculating any logical function on its own. We have also proposed quantum representation of the MOG gate with optimal quantum cost equal to 11. Then, it has been proved that MOG gate can be used to produce a cost efficient reversible full adder/subtractor cell in terms of reversible and quantum metrics. The proposed reversible full adder/subtractor design using MOG gate is a completely optimized circuit in terms of the number of reversible gates, the number of constant inputs, and the number of garbage outputs because it can work with the minimum possible amounts of these reversible metrics. Additionally, it is more efficient than the existing counterparts in terms of quantum cost. The full adder/subtractor cell is an important circuit in VLSI and digital signal processing applications. A lot of works have been done toward designing reversible full adder/subtractors in the literature; but there is no an optimized design with quantum implementation. To prove the applicability of the proposed design in large processing scales, we have constructed 8-bits reversible ripple carry full adder/subtractor circuit using MOG gates. Results have shown the superiority of our proposed design compared with other 8-bits similar designs.

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Section: Introductionmentioning

confidence: 99%

A Novel 4×4 Universal Reversible Gate as a Cost Efficient Full Adder/Subtractor in Terms of Reversible and Quantum Metrics

Moghimi

Reshadinezhad

2015

IJMECS

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“…As observed in (2), the transistor threshold voltage have an inverse relation with the CNT diameter. If m is assumed as zero, (3) is introduced for two CNFETs [5,22,23] …”

Section: Fig1 the Graphene Sheet To Be Formed In Carbon Nanotubementioning

confidence: 99%

“…These transistors have low power consumption and high speed in relation to that of the MOSFET. Another advantage of CNFET is its proper function at low input voltages [5,23,24].…”

Section: Fig1 the Graphene Sheet To Be Formed In Carbon Nanotubementioning

confidence: 99%

“…As it was mentioned, utilizing carbon nanotube field effect transistors could result in a higher performance of a circuit [5]. To implement the proposed three-operand multiplier applying nanotube technology, an AND gate and a full adder cell, presented by Reshadinezhad et al [23], are used as the main components. The AND gate and the full adder cell designed in CNFET technology, are depicted in Fig.…”

Section: Proposed Three-operand Multiplier Using Nanotube Technologymentioning

confidence: 99%

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Design and Implementation of a Three-operand Multiplier through Carbon Nanotube Technology

Reshadinezhad

Charmchi²,

Navi³

2015

IJMECS

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Abstract-Multiplication scheme is one of the most essential factors, which is time consuming. Designers and manufacturers of processors emphasis on methods which would not only perform the multiplication scheme in a rapid manner, but would reduce the physical aspect of the design as well; hence, a reduction in power consumption. Addition is one of the fundamental factors in multiplication. Pre-designing of circuits and transistors' levels used to be made through Metal Oxide Semiconductor Field Effect Transistor (MOSFET), but now, due to scaling and difficulties thereof, new technologies like Single Electron Transistor (SET), Quantum-dot Cellular Automata (QCA) and Carbon Nanotube Field Effect Transistor (CNFET) are introduced. Among the new technologies, CNFET has become center of attention due to similarities in electronic features in relation to MOSFET. A comparison made between CNFET with MOSFET technologies indicate that, power delay product (PDP) and power leakage can be less in nanotube transistors. Field effect transistor circuit's simulations are accomplished through HSPICE simulator. The simulation results indicate that this proposed Three-operand Carbon Nanotube Multiplier has a better performance in comparison with the threeoperand multiplication done on computers nowadays, which we call it classical multiplier in this article.

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“…Among these alternative technologies, the CNTFET is the most encouraging substitution for the conventional MOSFET family due to its similarities to MOSFET in terms of electrical properties and manufacturing process [26]. Up to now, many circuits have been successfully designed based on CNTFET technology, such as binary and ternary full adder cells, SRAM storage cells, multiple-valued logic circuits, and min-max circuits [27], [17]- [19], [21]- [24], [28]. The CNTFET can also be applied in polylactic acid structures [29].…”

Section: Introductionmentioning

confidence: 99%

An Efficient 5-Input Exclusive-OR Circuit Based on Carbon Nanotube FETs

Zarhoun

Moaiyeri

Farahani

et al. 2014

ETRI J

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The integration of digital circuits has a tight relation with the scaling down of silicon technology. The continuous scaling down of the feature size of CMOS devices enters the nanoscale, which results in such destructive effects as short channel effects. Consequently, efforts to replace silicon technology with efficient substitutes have been made. The carbon nanotube fieldeffect transistor (CNTFET) is one of the most promising replacements for this purpose because of its essential characteristics. Various digital CNTFET-based circuits, such as standard logic cells, have been designed and the results demonstrate improvements in the delay and energy consumption of these circuits. In this paper, a new CNTFET-based 5-input XOR gate based on a novel design method is proposed and simulated using the HSPICE tool based on the compact SPICE model for the CNTFET at the 32-nm technology node. The proposed method leads to improvements in performance and device count compared to the conventional CMOS-style design.Keywords: Nanotechnology, carbon nanotube fieldeffect transistor, CNTFET, high-performance circuits, CNTFET-based inverter, exclusive-OR gate, XOR gate. Manuscript received Jan. 13, 2013; revised Apr. 2, 2013; accepted Apr. 5, 2013. Ronak Zarhoun (phone: +98 2129904195, r.zarhoon@mail.sbu.ac.ir), Mohammad H. Moaiyeri (h_moaiyeri@sbu.ac.ir), and Samira S. Farahani (sa.shirinabadi@mail.sbu.ac.ir) are with the Nanotechnology and Quantum Computing Laboratory, Shahid Beheshti University, G.C., Tehran, Iran.Keivan Navi (corresponding author, navi@sbu.ac.ir, knavi@uci.edu) is with the Quantum Computing Laboratory, Shahid Beheshti University, G.C., Tehran, Iran, and is also with the Department of Electrical Engineering and Computer Science, University of California, Irvine, Irvine, CA, USA. I. IntroductionNo one can imagine today's world without the influence and power of computer technology, which dominates many aspects of people's lives, from such simple details as cell phones to such important and critical projects as those in aeronautics. All computer-based technological improvements are possible through computational functions, which are made up of precise logic gates. Such logic gates as NOT, NAND, NOR, and XOR are the main building blocks of logical functions [1], [2]. Considering these gates, the XOR gate plays a significant role in computational processors with low-power purposes and arithmetic circuits [3], [4], such as full adder cells [5], [6]-[8], parity bit generators and parity checkers [9], multipliers such as the polynomial basis multiplier [10], and comparator circuits [8], [11], [12]. High-speed XOR gates are needed for summation of partial products in multiplier circuits, and they are also used in MUX modules in arithmetic circuits [12].The most famous application of the XOR gate is in coding processes and data encryption or decryption, especially in AES (Advanced Encryption Standard) [1], which is sufficiently used in data communication. In design testing, it is used in built-in self-test structures [...

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An Energy-Efficient Full Adder Cell Using CNFET Technology

Cited by 35 publications

References 17 publications

A Novel 4×4 Universal Reversible Gate as a Cost Efficient Full Adder/Subtractor in Terms of Reversible and Quantum Metrics

A Novel 4×4 Universal Reversible Gate as a Cost Efficient Full Adder/Subtractor in Terms of Reversible and Quantum Metrics

Design and Implementation of a Three-operand Multiplier through Carbon Nanotube Technology

An Efficient 5-Input Exclusive-OR Circuit Based on Carbon Nanotube FETs

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