An Energy-Efficient and High Throughput in-Memory Computing Bit-Cell With Excellent Robustness Under Process Variations for Binary Neural Network

Abstract

In-memory computing (IMC) is a promising approach for energy cost reduction due to data movement between memory and processor for running data-intensive deep learning applications on the computing systems. Together with Binary Neural Network (BNN), IMC provides a viable solution for running deep neural networks at the edge devices with stringent memory and energy constraints. In this paper, we propose a novel 10T bit-cell with a back-end-of-line (BEOL) metal-oxide-metal (MOM) capacitor laid on pitch for in-memory computing. Our IMC bit-cell, when arranged in a memory array, performs binary convolution (XNOR followed by Bit-count operations) and binary activation generation operations. We show, when binary layers of BNN are mapped into our IMC arrays for MNIST digit classification, 98.75% accuracy with energy efficiency of 2193 TOPS/W and throughput of 22857 GOPS can be obtained. We determine the memory array size considering the word-line and bit-line nonidealities and show how these impact classification accuracy. We analyze the impact of process variations on classification accuracy and show how word-line pulse tunability provided by our design can be used to improve the robustness of classification under process variations.

AND8T SRAM Macro with Improved Linearity for Multi-Bit In-Memory Computing

“…As compared to the current/voltage based computation, charge-domain based computation is identified highly reliable, linear and stable and hence seems a great choice for the analog IMC implementation [17]. Therefore, to achieve a better linearity with enhanced SNR value through the charge-domain based computing, the AND8T includes a metal-oxide-metal capacitor (MOM cap) C C ∼ 1.6 fF in its read port between node X and RBL as shown in Fig.…”

Custom Memory Design for Logic-in-Memory: Drawbacks and Improvements over Conventional Memories

“…Many approaches to Logic-In-Memory can be found in literature; however, two main approaches can be distinguished. The first one can be classified as Near-Memory Computing (NMC) [2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18], since the memory inner array is not modified and logic circuits are added at the periphery of this; the second one can be denoted as Logic-in-Memory (LiM) [19][20][21][22][23][24][25][26][27][28], since the memory cell is directly modified by adding logic circuits to it.…”

“…Many applications can benefit from the IMC approach, such as machine learning and deep learning algorithms [4,6,[8][9][10][11][12]14,15,19,[21][22][23][24], but also general purpose algorithms [2,5,7,13,[16][17][18]20,25,26]. For instance: in [19], a 6T SRAM cell is modified by adding two transistors and a capacitor to it, in order to perform analog computing on the whole memory, which allows to implement approximated arithmetic operations for machine learning algorithms; in [18], logic layers consisting of latches and LUTs are interleaved with memory ones in an SRAM array, in order to perform different kinds of logic operations directly inside the array; in [26], the pass transistors of the 6T SRAM cell are modified to perform logic operations directly in the cell, which allows the memory to function as an SRAM, a CAM (Content Addressable Memory) or a LiM architecture.…”