Abstract:The Intel Itanium architecture uses a dedicated 32entry hardware table, the Advanced Load Address Table (ALAT) to support data speculation via an instruction set interface. This study presents an empirical evaluation of the use of the ALAT and data speculative instructions for several optimizing compilers. We determined what and how often compilers generated the different speculative instructions, and used the Itanium's hardware performance counters to evaluate their run-time behavior. We also performed a limi… Show more
“…Mock et al were able to prove by means of a modified C compiler, which forced data speculation on an Intel Itanium 2 CPU architecture where possible, that performance increases due to load value speculation [22] of up to 10% were achievable. On the other hand, the Itanium 2 roll-back mechanism, which is based on the Advanced Load Address Table (ALAT), a dedicated hardware structure that usually needs to be explicitly controlled by the programmer [20], produces performance losses of up to 5% under adverse conditions with frequent misspeculations.…”
“…Mock et al were able to prove by means of a modified C compiler, which forced data speculation on an Intel Itanium 2 CPU architecture where possible, that performance increases due to load value speculation [22] of up to 10% were achievable. On the other hand, the Itanium 2 roll-back mechanism, which is based on the Advanced Load Address Table (ALAT), a dedicated hardware structure that usually needs to be explicitly controlled by the programmer [20], produces performance losses of up to 5% under adverse conditions with frequent misspeculations.…”
“…Mock et al [2005] modified a compiler to force value speculation where possible on the Intel Itanium 2 CPU architecture. Their scheme relied on hardware support in the form of the Itanium's Advanced Load Address Table (ALAT) [McNairy and Soltis 2003].…”
Load value speculation has long been proposed as a method to hide the latency of memory accesses. It has seen very limited use in actual processors, often due to the high overhead of reexecuting misspeculated computations. We present PreCoRe, a framework capable of generating application-specific microarchitectures supporting load value speculation on reconfigurable computers. The article examines the lightweight speculation and replay mechanisms, the architecture of the actual data value prediction units as well as the impact on the nonspeculative parts of the memory system. In experiments, using PreCoRe has achieved speedups of up to 2.48 times over nonspeculative implementations.
“…Mock et al modified a compiler to force value speculation where possible on the Intel Itanium 2 CPU architecture [18]. Their scheme relied on hardware support in the form of the Itanium's Advanced Load Address Table (ALAT) [17].…”
The PreCoRe approach allows the automatic generation of application-specific microarchitectures from C, thus supporting complex speculative execution on reconfigurable computers. In this work, we present the PreCoRe capability of using data-value speculation to reduce the latency of memory reads, as well as the lightweight extension of static datapath controllers to the dynamic replay of misspeculated operations. The experimental evaluation considers the performance / area impact of the approach and also discusses the individual effects of combining different speculation mechanisms.
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.