An Empirical Model for Predicting SE Cross Section for Combinational Logic Circuits in Advanced Technologies

Jiang, Hui; Zhang, H.; Kauppila, J. S.; Massengill, L.W.; Bhuva, B. L.

doi:10.1109/tns.2017.2779885

Cited by 7 publications

(1 citation statement)

References 23 publications

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“…While an SEU can cause system malfunctions by data corruption, the error does not permanently damage the device as we can restore the original/new data by refresh or rewrite and hence referred to as a soft error. However, with technology scaling, the soft error rate (SER) in logic circuits is increasing significantly compared to the overall SER rate of the sequential circuits [18]. In fact, the per-bit logic SER has become comparable to that of the embedded memory at the 65nm node [1].…”

Section: Introductionmentioning

confidence: 99%

Low-Power Resonant Clocking Using Soft Error Robust Energy Recovery Flip-Flops

Islam

2018

J Electron Test

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An energy recovery or resonant clocking scheme is very attractive for saving the clock power in nanoscale ASICs and systems-on-chips, which have increased functionality and larger die sizes. The technology scaling followed Moore's law, that lowers node capacitance and supply voltage, making nanoscale integrated circuits more vulnerable to radiation-induced single event upsets (SEUs) or soft errors. In this work, we propose soft-error robust flipflops (FFs) capable of working with a sinusoidal resonant clock to save the overall chip power. The proposed conditional-pass Quatro (CPQ) FF and true single phase clock energy recovery (TSPCER) FF are based on a unique soft error robust latch, which we refer to as a Quatro latch. The proposed C 2 -DICE FF is based on a dual interlocked cell (DICE) latch. In addition to the storage cell, each FF consists of a unique input-stage and a two-transistor, two-input output buffer. In each FF with a sinusoidal clock, the transfer unit passes the data to the Quatro and DICE latches. The latches store the data values at two storage nodes and two redundant nodes, the latter enabling recovery from a particle-induced transient with or without multiple-node charge sharing. Postlayout simulations in 65nm CMOS technology show that the FF exhibits as much as 82% lower power-delay product compared to recently reported soft error robust FFs. We implemented 1024 proposed FFs distributed in an H-tree clock network driven by a resonant clock-generator that generates a 1-5 GHz sinusoidal clock signal. The simulation results show a power reduction of 93% on the clock tree and total power saving of up to 74% as compared to the same implementation using the conventional square-wave clocking scheme and FFs.

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Section: Introductionmentioning

confidence: 99%