An Embedded Vision Services Framework for Heterogeneous Accelerators

Gudis, Eduardo; Lu, Pullan; Berends, David; Kaighn, Kevin; Wal, G. van der; Buchanan, Gregory; Chai, Sek; Piacentino, Michael

doi:10.1109/cvprw.2013.90

Cited by 20 publications

(8 citation statements)

References 9 publications

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“…Required compute resources at edge compute node. Recent trends in vision are moving toward smart cameras, thereby enabling face recognition, motion detection, and other vision tools to be implemented to an increasing extent in hardware [10,20,28]. Consequently, simple embedded platforms with 500 MHz-1 GHz CPU are sufficient to implement the vision analytic functions at ECNs.…”

Section: Discussionmentioning

confidence: 99%

See 1 more Smart Citation

The Design and Implementation of a Wireless Video Surveillance System

Zhang

Chowdhery

Bahl

et al. 2015

Proceedings of the 21st Annual International Conference on Mobile Computing and Networking

219

128

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Internet-enabled cameras pervade daily life, generating a huge amount of data, but most of the video they generate is transmitted over wires and analyzed offline with a human in the loop. The ubiquity of cameras limits the amount of video that can be sent to the cloud, especially on wireless networks where capacity is at a premium. In this paper, we present Vigil, a real-time distributed wireless surveillance system that leverages edge computing to support real-time tracking and surveillance in enterprise campuses, retail stores, and across smart cities. Vigil intelligently partitions video processing between edge computing nodes co-located with cameras and the cloud to save wireless capacity, which can then be dedicated to Wi-Fi hotspots, offsetting their cost. Novel video frame prioritization and traffic scheduling algorithms further optimize Vigil's bandwidth utilization. We have deployed Vigil across three sites in both whitespace and Wi-Fi networks. Depending on the level of activity in the scene, experimental results show that Vigil allows a video surveillance system to support a geographical area of coverage between five and 200 times greater than an approach that simply streams video over the wireless network. For a fixed region of coverage and bandwidth, Vigil outperforms the default equal throughput allocation strategy of Wi-Fi by delivering up to 25% more objects relevant to a user's query.

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Section: Discussionmentioning

confidence: 99%

“…Gatework routers or NUC) with 500 MHz-1 GHz CPU have enough processing power to run image analysis functions for ECNs. Recent trends in vision are moving toward smart cameras, thereby enabling face recognition, motion detection, and other image analysis tools to be implemented to an increasing extent in hardware [10].…”

Section: Hardwarementioning

confidence: 99%

The Design and Implementation of a Wireless Video Surveillance System

Zhang

Chowdhery

Bahl

et al. 2015

Proceedings of the 21st Annual International Conference on Mobile Computing and Networking

219

128

View full text Add to dashboard Cite

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“…They were able to classify 320⇥240 images in 20 ms on the large FPGA which is 60⇥ faster than the mobile SoC. An embedded implementation of vision processing tasks on the Zynq platform is presented in [4], where multiple pre-compiled Acadia Vision IP cores are mapped to the FPGA fabric and interface with the ARMv7 host via VDMA blocks. For certain vision tasks like contrast normalization, image stabilization and moving target indication, they report processing rates of 15fps for 640⇥480 resolutions on the ZC702 and ZC706 boards .…”

Section: A Related Workmentioning

confidence: 99%

“…Only color filtering and morphological operations ran on the soft cores with the rest running on the ARMv7 CPU. Our MXP implementation targets a far more complex vision task than the ones reported in [4], [10] on the Zedboard while running at 5fps for 640⇥480 images. An alternative to Vivado HLS OpenCV library is presented in [8], where few OpenCV functions such as Gaussian Filter and Sobel Filter are implemented as optimizable nested loops.…”

Section: A Related Workmentioning

confidence: 99%

Energy-Efficient Acceleration of OpenCV Saliency Computation Using Soft Vector Processors

Hegde

Kapre

2015

2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines

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Soft vector processors in embedded FPGA platforms such as the VectorBlox MXP engine can match the performance and exceed the energy-efficiency of commercial off-the-shelf embedded SoCs with SIMD or GPU accelerators for OpenCV applications such as Saliency detection. We are also able to beat spatial hardware designs built from high-level synthesis while requiring significantly lower programming effort. These improvements are possible through careful scheduling of DMA operations to the vector engine, extensive use of line-buffering to enhance data reuse on the FPGA and limited use of scalar fallback for nonvectorizable code. The driving principle is to keep data and computation on the FPGA for as long as possible to exploit parallelism, data locality and lower the energy requirements of communication. Using our approach, we outperform all platforms in our architecture comparison while needing less energy. At 640⇥480 image resolution, our implementation of MXP soft vector processor on the Xilinx Zedboard exceeds the performance of the Jetson TK1-GPU by 1.5⇥ while needing 1.6⇥ less energy, Beaglebone Black by 4.7⇥ at 2.3⇥ less energy, Raspberry Pi by 9⇥ at 4⇥ less energy, and Intel Galileo by 28⇥ at 16⇥ less energy. Our vector implementation also outperforms Vivado HLS generated OpenCV library implementation by 1.5⇥.

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“…In this paper, two videos are captured by CCD and LWIR cameras and fused by implementing DT-CWT fusion algorithms in Xilinx Virtex-II environment. Gudis et al [11] built an embedded vision service framework on ZYNQ SoC with a "plug-andplay" capability to allow the service-based software to take advantage of the hardware acceleration blocks available and perform the remainder of the processing in software. These designs share some similarities with our system but focus on the fusion quality more than the performance and energy efficiency.…”

Section: Related Workmentioning

confidence: 99%

Computing to the Limit with Heterogeneous CPU-FPGA Devices in a Video Fusion Application

Nunez-Yanez

2016

Lecture Notes in Computer Science

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Abstract. This paper presents a complete video fusion system with hardware acceleration and investigates its performance and energy optimization. The video fusion application is based on the Dual-Tree Complex Wavelet Transforms (DT-CWT). Video fusion combines information from different spectral bands into a single representation and advanced algorithms based on wavelet transforms are compute and energy intensive. In this work the transforms are mapped to a hardware accelerator using high-level synthesis tools for the FPGA resulting in an increase of performance of the system by a factor of 3. In a second stage the hardware engine is transformed with a set of tools and detector blocks that allow the CPU device to monitor and pre-detect timing failures in the FPGA fabric. The CPU device can control the voltage and frequency of the FPGA and obtain a new working point with reducing power requirements by approximately 70% with an equivalent performance level. This results in an energy proportional computing system in which only the energy required to maintain a required level of performance is used.

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An Embedded Vision Services Framework for Heterogeneous Accelerators

Cited by 20 publications

References 9 publications

The Design and Implementation of a Wireless Video Surveillance System

The Design and Implementation of a Wireless Video Surveillance System

Energy-Efficient Acceleration of OpenCV Saliency Computation Using Soft Vector Processors

Computing to the Limit with Heterogeneous CPU-FPGA Devices in a Video Fusion Application

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