An Embedded CNN Implementation for On-Device ECG Analysis

Burger, Alwyn; Qian, Chao; Schiele, Gregor; Helms, Domenik

doi:10.1109/percomworkshops48775.2020.9156260

Cited by 21 publications

(14 citation statements)

References 3 publications

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“…The BN parameters in Fig. 4 6)- (8). To avoid disarranging the DRAM data layout for adjacent Conv layers, we load data tile by tile using the same data format as that in Conv layers.…”

Section: The Forward Propagation Of a Bn Layermentioning

confidence: 99%

“…We select the batch size 𝐵 as 4 and the DMA stream width as 128 bits. We adopt the results using the BCHW data layout and the results using the BHWC data layout as baselines ([𝑇𝑚 𝐵𝑎𝑠𝑒 ,𝑇 𝑛 𝐵𝑎𝑠𝑒 ] = [32,8]). The BCHW pattern does not involve any optimization.…”

Section: Effectiveness Of the Data Reshaping Approachmentioning

confidence: 99%

“…In medical applications, an FPGA-based low-latency multi-layer perception (MLP) processor for real-time cancer detection has been developed, since FPGA-based design can directly interface with sensors, display devices, and reduce data movement delays [7]. Burger et al applied an FPGA-based embedded device to monitor users' electrocardiograms (ECGs) in a pervasive internet-of-things (IoT) system [8]. FPGAs have also been well performed in other areas such as agricultural robots [9], UAVs [10], etc.…”

Section: Introductionmentioning

confidence: 99%

“…For example, in some medical applications such as home monitoring [13], long-term ECG monitoring [14], etc., the distinction of different users' physical conditions will impact data distribution, so models need to be fine-tuned based on specific users. The system in [8] utilized cloud services to log a user's condition over time and continuously improve the system's performance. It would be more effective if models could be directly updated on the FPGA device.…”

Section: Introductionmentioning

confidence: 99%

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EF-Train: Enable Efficient On-device CNN Training on FPGA Through Data Reshaping for Online Adaptation or Personalization

Tang¹,

Zhang²,

Zhou³

et al. 2022

Preprint

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Conventionally, DNN models are trained once in the cloud and deployed in edge devices such as cars, robots, or unmanned aerial vehicles (UAVs) for real-time inference. However, there are many cases that require the models to adapt to new environments, domains, or new users. In order to realize such domain adaption or personalization, the models on devices need to be continuously trained on the device. In this work, we design EF-Train, an efficient DNN training accelerator with a unified channel-level parallelism-based convolution kernel that can achieve end-to-end training on resource-limited low-power edge-level FPGAs. It is challenging to implement on-device training on resource-limited FPGAs due to the low efficiency caused by different memory access patterns among forward, backward propagation, and weight update. Therefore, we developed a data reshaping approach with intra-tile continuous memory allocation and weight reuse. An analytical model is established to automatically schedule computation and memory resources to achieve high energy efficiency on edge FPGAs. The experimental results show that our design achieves 46.99 GFLOPS and 6.09 GFLOPS/W in terms of throughput and energy efficiency, respectively.

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“…The BN parameters in Fig. 4 6)- (8). To avoid disarranging the DRAM data layout for adjacent Conv layers, we load data tile by tile using the same data format as that in Conv layers.…”

Section: The Forward Propagation Of a Bn Layermentioning

confidence: 99%

Section: Effectiveness Of the Data Reshaping Approachmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

EF-Train: Enable Efficient On-device CNN Training on FPGA Through Data Reshaping for Online Adaptation or Personalization

Tang¹,

Zhang²,

Zhou³

et al. 2022

Preprint

View full text Add to dashboard Cite

show abstract

“…However, in practice this approach is limited by the availability and range of the wireless connection. Burger et al present an approach for an embedded ECG classification use case realizing NNs on small FPGA devices [9]. However, inherently the reconfigurability of the applied FPGA devices adds overhead in hardware and limits the optimization potential to apply beneficial improvements like power gating in parts of the design or using novel memory technology.…”

Section: Related Workmentioning

confidence: 99%

A Framework for Ultra Low-Power Hardware Accelerators Using NNs for Embedded Time Series Classification

Reiser

Reichel

Pechmann

et al. 2021

JLPEA

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In embedded applications that use neural networks (NNs) for classification tasks, it is important to not only minimize the power consumption of the NN calculation, but of the whole system. Optimization approaches for individual parts exist, such as quantization of the NN or analog calculation of arithmetic operations. However, there is no holistic approach for a complete embedded system design that is generic enough in the design process to be used for different applications, but specific in the hardware implementation to waste no energy for a given application. Therefore, we present a novel framework that allows an end-to-end ASIC implementation of a low-power hardware for time series classification using NNs. This includes a neural architecture search (NAS), which optimizes the NN configuration for accuracy and energy efficiency at the same time. This optimization targets a custom designed hardware architecture that is derived from the key properties of time series classification tasks. Additionally, a hardware generation tool is used that creates a complete system from the definition of the NN. This system uses local multi-level RRAM memory as weight and bias storage to avoid external memory access. Exploiting the non-volatility of these devices, such a system can use a power-down mode to save significant energy during the data acquisition process. Detection of atrial fibrillation (AFib) in electrocardiogram (ECG) data is used as an example for evaluation of the framework. It is shown that a reduction of more than 95% of the energy consumption compared to state-of-the-art solutions is achieved.

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