An Architecture for Solving the Eigenvalue Problem on Embedded FPGAs

Burger, Alwyn; Urban, Patrick; Boubin, Jayson; Schiele, Gregor

doi:10.1007/978-3-030-52794-5_3

Cited by 5 publications

(2 citation statements)

References 21 publications

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“…Specialized hardware designs for eigensolvers are limited to resolving the full eigenproblem on small dense matrices, through the QR-Householder Decomposition and Jacobi eigenvalue algorithm. Most formulations of the Jacobi algorithm [20], [21] leverage Systolic Array, a major building block of high performance domain-specific architectures from their inception [22] to more recent results [23]- [25]. However, hardware designs of the Jacobi algorithm based on SA cannot scale to large matrices, as the resource utilization scales linearly with the size of the matrix.…”

Section: Related Workmentioning

confidence: 99%

“…The Jacobi eigenvalue algorithm has sought many formulations to improve either its parallelism or its resource utilization. The best-known formulation of the algorithm was proposed by Brent and Luk [33] and has been the standard for implementing the algorithm on FPGA to this day [20], [21]. Our design improves this formulation with a more resourceefficient procedure for interchanging rows and columns, and its structure is shown in Figure 5.…”

Section: B the Jacobi Eigenvalue Algorithmmentioning

confidence: 99%

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Solving Large Top-K Graph Eigenproblems with a Memory and Compute-optimized FPGA Design

Sgherzi¹,

Parravicini²,

Siracusa³

et al. 2021

Preprint

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Large-scale eigenvalue computations on sparse matrices are a key component of graph analytics techniques based on spectral methods. In such applications, an exhaustive computation of all eigenvalues and eigenvectors is impractical and unnecessary, as spectral methods can retrieve the relevant properties of enormous graphs using just the eigenvectors associated with the Top-K largest eigenvalues.In this work, we propose a hardware-optimized algorithm to approximate a solution to the Top-K eigenproblem on sparse matrices representing large graph topologies. We prototype our algorithm through a custom FPGA hardware design that exploits HBM, Systolic Architectures, and mixed-precision arithmetic. We achieve a speedup of 6.22x compared to the highly optimized ARPACK library running on an 80-thread CPU, while keeping high accuracy and 49x better power efficiency.

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