An Elitist Non-Dominated Sorting Based Genetic Algorithm for Simultaneous Area and Wirelength Minimization in VLSI Floorplanning

Abstract

VLSI floorplanning in the gigascale era must deal with multiple objectives including wiring congestion, performance and reliability. Genetic Algorithms lend themselves naturally to multi-objective optimization. In this paper, a multi-objective genetic algorithm is proposed for floorplanning that simultaneously minimizes area and total wirelength. The proposed genetic floorplanner is the first to use non-domination concepts to rank solutions. Two novel crossover operators are presented that build floorplans using good sub-floorplans. The efficiency of the proposed approach is illustrated by the 18% wirelength savings and 4.6% area savings obtained for the GSRC benchmarks and 26% wirelength savings for the MCNC benchmarks for a marginal 1.3% increase in area when compared to previous floorplanners that perform simultaneous area and wirelength minimization.

SMT-Based Placement for System-on-Chip Design

“…Besides that, several approaches based on GAs have been proposed for the domain of macro placement. To this end, approaches like [11], [12] utilize randomness and heuristics. However, heuristic-based approaches are not capable to guarantee that the macro placement which is based on an optimal die area is found.…”

An exact algorithm for wirelength optimal placements in VLSI design

“…The approaches used often rely on heuristics similar to the methods that are also applied for area minimization. For example, Tang and Sebastian [43] use a genetic algorithm to optimize over O-trees, Fernando and Katkoori [11] use sequence pairs, and Lin et al [28] use B*-trees. Yan and Chu [47] use generalized slicing trees in combination with local operations to optimize the wirelength.…”

“…Many works present packing algorithms and do not discuss wirelength minimization. Moreover, works that do address wirelength most often do not use the original die area but scale or completely change it in order to reduce whitespace [4,5,6,11,20,28,43,49]. In these cases it is usually not clear how the locations of the original IO pads are adjusted or if they are included at all.…”

Non Slicing Floorplan Representations in VLSI Floorplanning: A Summary

“…Pradeep Fernando and Srinivas Katkoori (2008) [25] proposed a multi-objective genetic algorithm for floorplanning that simultaneously minimizes area and total wirelength. The proposed genetic floorplanner is the first to use non-domination concepts to rank solutions.…”