An electromigration and related resistance increase phenomenon on a tungsten filled via hole structure

Matsuoka, F.; Hama, K.; Nakata, R.; Kanzaki, K.

doi:10.1109/vmic.1988.14230

Cited by 2 publications

(1 citation statement)

References 6 publications

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“…However, stability and possible degradation phenomena of such a metallization scheme have to be investigated carefully, especially in view of subsequent thermal processing steps. Whereas a lot of work has been done to elucidate the W/A1 interface problems (8), few efforts have been made to understand the ternary layer system W/WSiJA1(Si, Ti) which is the essential element of a via plug technique based on a blanket tungsten process (Fig. 1).…”

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A Study of Interfacial Reactions in W / WSi x / Al ( Si , Ti ) Via Hole Metallization

Bertagnolli

Mitwalsky

1991

J. Electrochem. Soc.

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Planar vertical interconnects and low resistivity track lines are stringent requirements for future very large scale integrated (VLSI) and ultra large scale integrated (ULSI) multilevel metallizations schemes. A blanket chemically vapor deposited tungsten-plug technique involving an adhesion promoting layer of WSi., in combination with an aluminum track scheme is a very promising choice. Stability and metallurgical interactions of such a metallization system are of major concern. Many investigations have focused on the interface W/AI(Si, Ti), elucidating the barrier function of W against indiffusion of A1. Equivalent investigations regarding possible interfacial reactions of the triple-layer system W/WSiJAI(Si, Ti) are rare. By using transmission electron microscopy (TEM), energy-dispersive x-ray spectroscopy (EDX), and Auger electron spectroscopy (AES) a detailed analysis of samples deposited at 400 and 450~ respectively, and of samples additionally annealed at 450~ was performed. The WSi.~. forms an amorphous matrix with small crystalline precipitates identified as ~-tungsten. The interfaces AI(Si, Ti)/WSi,. and WSiJW are free from any detrimental layer. Indiffusion of A1 into the amorphous WSix layer is found to take place at typical VLSI annealing temperatures of 450~ resulting in a high A1 concentration within this layer. Extensive voids in the adjacent A1 regions are the consequence of this mass flow leading to reliability risks due to electromigration at the remaining contact areas.

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A Study of Interfacial Reactions in W / WSi x / Al ( Si , Ti ) Via Hole Metallization

Bertagnolli

Mitwalsky

1991

J. Electrochem. Soc.

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A comparison of basic 94 GHz planar transmission line resonators in commercial BiCMOS back-end-of-line processes

Stander

2014

2014 International Conference on Actual Problems of Electron Devices Engineering (APEDE)

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-A comparative simulation study of planar 94 GHz resonators in a typical BiCMOS BEOL stack-up is presented, with the effect of chip passivation included. It is shown that Q-factors of between 3 and 15 can be obtained, depending on transmission medium and ground plane layer choice. Straight half-wavelength and shorted quarter-wavelength microstrip resonators are shown to outperform CPW, GCPW and hairpin resonators, with highest Qfactors obtained where the lowest available metallization layer is used as ground plane. Q-factors of above 10 may also be achieve in the absence of any ground plane in CPW, which may be implemented in processes (such as GaAs or GaN) where multiple metallization layers are not readily available. IntroductionMillimeter-wave receivers (30 -110 GHz) have found widespread terrestrial commercial application in passive imaging [1] and automotive RADAR [2] due to the compact size and sharp resolution over short distances. Due to congestion in traditional GSM and LTE frequencies, attention is being turned to the under-utilized mm-wave spectrum for short-and medium-range communications applications [3].Monolithic integration of these future systems [4] presents significant cost and size advantages as opposed to waveguide implementations [5], with Silicon-Germanium Bipolar Complementary Metal-Oxide-Semiconductor (SiGe BiCMOS) providing full mixed-signal mm-wave system-on-chip integration possibilities [6]. To enable complex signal routing for system-onchip applications, the back-end-of-line (BEOL) of RFCMOS and BiCMOS feature multiple metallization layers [6] which may be used to implement complex 2.5D distributed elements.A significant drawback to complete on-chip systems is the high losses associated with passive circuitry surrounding the active transistors on the semiconductor wafer [7]. This is especially problematic in the implementation of on-chip filters, since the mid-band filter insertion loss is inversely proportional to the achievable resonator Q-factor [8]. Typical achieved unloaded quality factors (Q-factors) for on-chip resonators at V-and W-band frequencies have been demonstrated only up to 83 [9] for compound transmission line resonators, 43 for shielded transmission line resonators [10], 25 for single transmission line resonators [11] and below 15 for LC tanks [11].

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An electromigration and related resistance increase phenomenon on a tungsten filled via hole structure

Cited by 2 publications

References 6 publications

A Study of Interfacial Reactions in W / WSi x / Al ( Si , Ti ) Via Hole Metallization

A Study of Interfacial Reactions in W / WSi x / Al ( Si , Ti ) Via Hole Metallization

A comparison of basic 94 GHz planar transmission line resonators in commercial BiCMOS back-end-of-line processes

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