An Efficient Universal Addition Scheme for All Hybrid-Redundant Representations with Weighted Bit-Set Encoding

Abstract

Redundant and hybrid-redundant number representations are used extensively to speed up arithmetic operations within general-purpose and special-purpose digital systems, with the latter (containing both redundant and nonredundant digits) offering cost advantages over fully redundant systems. We use weighted bit-set (WBS) encoding as a paradigm for uniform treatment of five previously studied variants of hybrid-redundant systems. We then extend the class of hybrid redundant numbers to coincide with the entire set of canonical WBS numbers by allowing an arbitrary nonredundant position, heretofore restricted to ordinary bits (posibits), to hold a negatively weighted bit (negabit). This flexibility leads to interesting and useful symmetric variants of hybrid-redundant representations. We provide a high-level circuit design, based solely on binary full-adders, for a constant-time universal hybrid-redundant adder capable of producing a canonical WBS-encoded sum of two canonical WBS (or extended hybrid) numbers. This is made possible by the use of conventional binary full-adders for reducing any collection of three posibits and negabits, where negabits use an inverted encoding. We compare our adder to previous designs, showing advantages in speed, cost, and regularity. Furthermore we explore representationally closed addition schemes, holding the benefit of greater regularity and reusability, and provide high-level representationally closed designs for all the previously studied variants of hybrid redundancy and for the new symmetric variants introduced here. Finally, we present a new functionality for a conventional (4; 2) compressor in combining any collection of five equally weighted negabits and posibits, and show its utility in the design of multipliers for extended hybridredundant numbers.

Posibits, negabits, and their mixed use in efficient realization of arithmetic algorithms

“…However, because of the ad hoc approach, the design effort is much greater and the resulting circuits cannot benefit from performance improvements on standard cells. Any available (4; 2)-compressor circuit, on the other hand, properly handles any 5-collection of posibits and IE-negabits in its inputs [20]. There are also other highly optimized compressors, exemplified by (5; 2) compressors [20], that may prove beneficial in reducing mixed posibit/negabit matrices where the depth is not a multiple of 4.…”

“…Any available (4; 2)-compressor circuit, on the other hand, properly handles any 5-collection of posibits and IE-negabits in its inputs [20]. There are also other highly optimized compressors, exemplified by (5; 2) compressors [20], that may prove beneficial in reducing mixed posibit/negabit matrices where the depth is not a multiple of 4. This is yet another confirmation that the use of highly optimized standard cells is preferable whenever possible.…”

“…We have previously used IE-negabits and WBS encoding for the implementation of efficient arithmetic circuits with redundant and hybrid-redundant representations [20], [22]. Implementation of BSD addition, by means of off-the-shelf (4; 2)-compressors, was mentioned in Section 3 (Fig.…”

Redundant-Digit Floating-Point Addition Scheme Based on a Stored Rounding Value

“…Logically, we use 0 for the smaller and 1 for the larger of the two twit values, a convention leading to inverted encoding of negabits (0 denotes À1 and 1 denotes 0), complementary to the common usage. Such encodings ( Table 2) have been shown to result in efficient, VLSIfriendly adder designs [11], [18].…”

“…As another example, the stored-posibit-transfer (SPT) encoding [18] of the radix-16 digit set [À8, 8], where there can be at most one leading insignificant 1 (À1) followed to the right by À8 (8), obviates the need for any complex provision to convert leading insignificant nonzero digits. But the active hardware replication factor of the SPT adder is only modestly less than that in the design of Fahmy and Flynn.…”