An efficient sparse conjugate gradient solver using a Beneš permutation network

Abstract

Abstract-The conjugate gradient (CG) is one of the most widely used iterative methods for solving systems of linear equations. However, parallelizing CG for large sparse systems is difficult due to the inherent irregularity in memory access pattern. We propose a novel processor architecture for the sparse conjugate gradient method. The architecture consists of multiple processing elements and memory banks, and is able to compute efficiently both sparse matrix-vector multiplication, and other dense vector operations. A Beneš permutation network with an optimised control scheme is introduced to reduce memory bank conflicts without expensive logic. We describe a heuristics for offline scheduling, the effect of which is captured in a parametric model for estimating the performance of designs generated from our approach.

Cask

“…Although early implementations introduced too much overhead [12], recent preprocessing, scheduling and partitioning techniques have been employed successfully [2,7]. Pre-processing has become essential for modern SpMV based applications and it is also used in our approach to enable partitioning and blocking.…”

“…For the HPC community to use FPGAs effectively, SpMV kernels need to have good performance. However, the dynamic nature of the data flow in SpMV [2,3] requires expensive and complex circuitry and it becomes a challenge to achieve effective use of arithmetic and logic resources and on-chip and off-chip memory bandwidth. Furthermore, performance varies greatly based on the matrix instance [4][5][6].…”

Optimising Sparse Matrix Vector multiplication for large scale FEM problems on FPGA

“…In this regard, FPGAs may have a considerable advantage compared to general purpose architectures: the fine degree of customisation available can be used to directly and carefully orchestrate data movement on and off-chip resulting in good performance on the SpMV kernel [4]- [6]. Furthermore, when using FPGAs there is great potential for application and domain driven customisation: wordlengths, reduction circuits, memory controller infrastructure can all be optimised to direct resources to the most critical component [7]- [11].…”

“…[16] proposes one of the first parametric designs for floating point SpMV and demonstrates how the flexibility of FPGAs can be used to achieve good performance compared to general purpose systems. More recently, the focus has shifted to efficient use of on-chip memory resources and DRAM bandwidth utilisation [5], [7], [9]. Recently, compression techniques have been proposed to improve the performance on memory bound matrices [8], [17] The constant sparsity structure in the context of iterative methods has also been exploited to optimise FPGA architectures for SpMV [18].…”

“…Recently, compression techniques have been proposed to improve the performance on memory bound matrices [8], [17] The constant sparsity structure in the context of iterative methods has also been exploited to optimise FPGA architectures for SpMV [18]. Static one-off pre-processing techniques are cost-effective for FPGA implementations if they can lead either to a simplified architecture [5], [7], [19] or reduced communication overhead [8], [17]. Linear or log-linear preprocessing techniques with good performance in practice, such as the method used in this work for extracting matrix properties, have been found to be effective.…”