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Grigoras, Paul; Burovskiy, Pavel; Luk, Wayne

doi:10.1145/2847263.2847338

Cited by 17 publications

(6 citation statements)

References 18 publications

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“…However, they assume that the memory access of the vector is sequential. [10] proposes a framework that can generate a specific accelerator for each matrix. However, this framework requires a quite long preprocessing time.…”

Section: Related Workmentioning

confidence: 99%

Efficient FPGA-Based Sparse Matrix–Vector Multiplication With Data Reuse-Aware Compression

Liu

2023

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Section: Related Workmentioning

confidence: 99%

Efficient FPGA-Based Sparse Matrix–Vector Multiplication With Data Reuse-Aware Compression

Liu

2023

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…However, each processing element holds a copy of the result vector which has a similar overhead as holding multiple copies of the input vector. [20] proposes a framework that can generate a specific accelerator for each matrix. The framework automatically determines the off-chip data layout and on-chip hardware designs.…”

Section: Related Workmentioning

confidence: 99%

“…Select as many elements as possible from C S ; end if 25: end while column if the longest column has remaining elements (line 10). If the buffered vector value is available, we try to form a group with elements from the buffered column and the shortest column (line [15][16][17][18][19][20][21][22][23]. If the group has not been fulfilled, we use elements from the current shortest column to fill it (line [21][22].…”

Section: Format Conversionmentioning

confidence: 99%

“…[19][20][21][22][23][24][3][25].SpMV mainly includes multiplications between nonzero matrix elements and the corresponding vector values and accumulations of products belonging to the same row. Note that nonzero elements are transferred from the off-chip DDR to the FPGA chip and the number of nonzero elements is determined by the available memory bandwidth.…”

mentioning

confidence: 99%

“…Then, each remaining element in the columns is paired with single elements to form a group and the group is appended to M r (line[11][12]. When reusable columns are exhausted or totalCapacity is no less than 0, we begin to reorder the remaining nonzero matrix elements following Rule 1 and Rule 3 (line[16][17][18][19][20]. Following Rule 3,…”

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confidence: 99%

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Accelerating sparse matrix operations on FPGAs with on/off-chip memories

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This thesis contains material from 5 paper(s) published or accepted in the following peer-reviewed journal and conferences in which I am listed as an author. Chapter 3 is partially published as Shiqing Li, Di Liu and Weichen Liu, "Optimized Data Reuse via Reordering for Sparse Matrix-Vector Multiplication on FP-GAs" in International Conference on Computer-Aided Design (ICCAD) 2021 and is partially published as Shiqing Li, Di Liu and Weichen Liu, "Efficient FPGAbased Sparse Matrix-Vector Multiplication with Data Reuse-aware Compression" in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) 2023. The contributions of the co-authors are as follows: • Prof. Weichen Liu provided the initial idea of accelerating sparse-matrix dense-vector multiplication on embedded FPGAs. • I proposed the data reordering algorithm and the data reuse-aware compression. Meanwhile, I conduct experiments on FPGAs. Dr. Di Liu and Prof. Weichen Liu provided insightful comments about the idea and experiments. • I drafted the manuscript. Dr. Di Liu and Prof. Weichen Liu helped polish the manuscript. Chapter 4 is partially published as Shiqing Li and Weichen Liu, "Accelerating Gustavson-based SpMM on Embedded FPGAs with Element-wise Parallelism and Access Pattern-aware Caches", in Design, Automation and Test in Europe (DATE) 2023 and is partially published as Shiqing Li, Shuo Huai and Weichen Liu, "An Efficient Gustavson-based Sparse Matrix-matrix Multiplication Accelerator on Embedded FPGAs", in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) 2023.The contributions of the co-authors are as follows:• Prof. Weichen Liu provided the initial idea of accelerating sparse-matrix sparse-matrix multiplication on embedded FPGAs. • I proposed to perform the Gustavson's algorithm with element-wise parallelism, access pattern-aware caches and optimized mergers. I further conduct experiments on FPGAs. Shuo Huai helped conduct experiments. • I drafted the manuscript. Prof. Weichen Liu and Shuo Huai helped polish the manuscript.

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dfesnippets: An Open-Source Library for Dataflow Acceleration on FPGAs

Grigoras

Burovskiy

Arram

et al. 2017

Lecture Notes in Computer Science

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Abstract. Highly-tuned FPGA implementations can achieve significant performance and power efficiency gains over general purpose hardware. However the limited development productivity has prevented mainstream adoption of FPGAs in many areas such as High Performance Computing. High level standard development libraries are increasingly adopted in improving productivity. We propose an approach for performance critical applications including standard library modules, benchmarking facilities and application benchmarks to support a variety of use-cases. We implement the proposed approach as an open-source library for a commercially available FPGA system and highlight applications and productivity gains.

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Cask

Cited by 17 publications

References 18 publications

Efficient FPGA-Based Sparse Matrix–Vector Multiplication With Data Reuse-Aware Compression

Efficient FPGA-Based Sparse Matrix–Vector Multiplication With Data Reuse-Aware Compression

Accelerating sparse matrix operations on FPGAs with on/off-chip memories

dfesnippets: An Open-Source Library for Dataflow Acceleration on FPGAs

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